H
He Peng
Researcher at University of California, San Diego
Publications - 11
Citations - 142
He Peng is an academic researcher from University of California, San Diego. The author has contributed to research in topics: Speedup & Very-large-scale integration. The author has an hindex of 8, co-authored 11 publications receiving 140 citations. Previous affiliations of He Peng include University of California, Berkeley.
Papers
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Proceedings ArticleDOI
Parallel transistor level circuit simulation using domain decomposition methods
He Peng,Chung-Kuan Cheng +1 more
TL;DR: An efficient parallel transistor level full-chip circuit simulation tool with SPICE-accuracy with orders of magnitude speedup over SPICE is observed for sets of large-scale VLSI circuits.
Proceedings ArticleDOI
Reliability aware through silicon via planning for 3D stacked ICs
Amirali Shayan,Xiang Hu,He Peng,Chung-Kuan Cheng,Wenjian Yu,Mikhail Popovich,Thomas R. Toms,Xiaoming Chen +7 more
TL;DR: This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs) by modeled and extracted in frequency domain which includes the impact of skin effect.
Proceedings ArticleDOI
3D power distribution network co-design for nanoscale stacked silicon ICs
Amirali Shayan,Xiang Hu,He Peng,Mikhail Popovich,Wanping Zhang,Chung-Kuan Cheng,Lew G. Chua-Eoan,Xiaoming Chen +7 more
TL;DR: In this paper, the authors proposed an efficient flow for the analysis and co-design of large 3D power distribution networks (3D PDN), which can take advantage of parallel computing.
Proceedings ArticleDOI
Parallel transistor level full-chip circuit simulation
He Peng,Chung-Kuan Cheng +1 more
TL;DR: A fully parallel transistor level full-chip circuit simulation tool with SPICE-accuracy for general circuit designs and the proposed overlapping domain decomposition approach partitions the circuit into a linear subdomain and multiple non-linear subdomains based on circuit non- linearity and connectivity.
Journal ArticleDOI
Two-Stage Newton–Raphson Method for Transistor-Level Simulation
TL;DR: An efficient transistor-level simulation tool with SPICE-accuracy for deep-submicrometer very large-scale integration circuits with strong-coupling effects with orders-of-magnitude speedup over Berkeley SPICE3 is observed.