Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A chip package includes: a substrate; a signal pad and a ground pad disposed on the substrate; a first and a second conducting layers disposed on the substrate and electrically connected to the signal pad and the ground pad, respectively, wherein the first and the second conducting layers extend from an upper surface of the substrate towards a lower surface of the substrate along a first and a second side surfaces of the substrate, respectively, and the first and the second conducting layers protrude from the lower surface; and a protection layer disposed on the substrate, wherein the protection layer completely covers the entire portion of the first conducting layer located on the first side surface of the substrate, and the entire portion of the second conducting layer located on the second side surface of the substrate is not covered by the protection layer.

Chip package and method for forming the same

This silicon-carbide semiconductor device (101) has a silicon-carbide substrate (10), a main electrode (52), a first barrier layer (70a), and a wiring layer (60). The main electrode (52) is provided directly on top of the silicon-carbide substrate (10). The first barrier layer (70a) is provided on top of the main electrode (52) and is made from a conductive material that does not contain aluminum. The wiring layer (60) is provided on top of the first barrier layer (70a), is isolated from the main electrode (52) by the first barrier layer (70a), and is made from a material that does contain aluminum.

Silicon carbide semiconductor device

Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described.

Structures and methods for improving trench-shielded semiconductor devices and schottky barrier rectifier devices

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Trench-based power semiconductor devices with increased breakdown voltage characteristics

A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.

Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration

Production of a transistor arrangement comprises: (a) inserting a trench (6) in a process layer (2) of a semiconductor substrate (7; (b) providing a field electrode (63) and a gate electrode (62) separately from each other and electrically insulated by the process layer; and (c) forming a drift zone (21), a channel zone (22) and a source zone (23) in the process zone. Either the source zone or the channel zone is produced after the trench is formed in the semiconductor substrate. An Independent claim is also included for a trench transistor cell formed in a semiconductor substrate. Preferably after inserting the trench in the process layer, the trench is lined with a first dielectric layer and the field electrode is arranged on sections of the trench lined with the dielectric layer. After producing the field electrode, a gate dielectric layer is formed on sections of the trench wall and a second dielectric layer on the field electrode.

Production of a transistor arrangement comprises inserting a trench in a process layer of a semiconductor substrate, and forming a drift zone, a channel zone and a source zone in the process zone

The invention relates to a method for fabricating a transistor arrangement having at least one trench transistor cell, which has a gate electrode (62) and a field electrode (63) arranged in a trench (6) below the gate electrode (62), in which trenches (6) are introduced into a semiconductor substrate (7) and a drift zone (21), a channel zone (22) and a source zone (23) are in each case provided in the semiconductor substrate (7). According to the invention, the source zone (23) and/or the channel zone (22) are formed at the earliest after the introduction of the trenches (6) into the semiconductor substrate (7) by implantation and diffusion.

Method for fabricating a transistor arrangement having trench transistor cells having a field electrode

A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.

Controlling the reflow behaviour of BPSG films and devices made thereof

This invention relates to a transistor device (1) with a gate electrode (4) in a vertical gate trench (5), wherein the gate electrode (4) comprises a silicon gate region (8) and a metal inlay region (9), the silicon gate region (8) forming at least a section (7.1) of a sidewall (7) of the gate electrode (4), and the metal inlay region (9) extending up from a lower end (10) of the gate electrode (4).

Heimo Hofer

Papers

Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration

Production of a transistor arrangement comprises inserting a trench in a process layer of a semiconductor substrate, and forming a drift zone, a channel zone and a source zone in the process zone

Method for fabricating a transistor arrangement having trench transistor cells having a field electrode

Controlling the reflow behaviour of BPSG films and devices made thereof

Semiconductor transistor device and method of manufacturing the same