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Henry Selvaraj

Researcher at University of Nevada, Las Vegas

Publications -  117
Citations -  1363

Henry Selvaraj is an academic researcher from University of Nevada, Las Vegas. The author has contributed to research in topics: Functional decomposition & Logic synthesis. The author has an hindex of 18, co-authored 116 publications receiving 1247 citations. Previous affiliations of Henry Selvaraj include Mepco Schlenk Engineering College & Monash University, Clayton campus.

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Book ChapterDOI

Distributed Processing Applications for UAV/drones: A Survey

TL;DR: This paper surveys the applications implemented over cooperative teams of UAVs that operate as distributed processing systems and the distributed processing system principles.
Journal ArticleDOI

Brain MRI Slices Classification Using Least Squares Support Vector Machine

TL;DR: Advanced classification techniques based on Least Squares Support Vector Machines (LS-SVM) are proposed and applied to brain image slices classification using features derived from slices and compared with other classifiers like SVM with linear and nonlinear RBF kernels, RBF classifier, Multi Layer Perceptron (MLP) classifier and K-NN classifier.
Journal ArticleDOI

A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis

Tadeusz Luba, +1 more
- 01 Jan 1995 - 
TL;DR: An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices.
Journal ArticleDOI

An application of functional decomposition in ROM-based FSM implementation in FPGA devices

TL;DR: The paper presents a general method for the synthesis targeted to implementation of sequential circuits using embedded memory blocks based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block.
Book ChapterDOI

A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing

TL;DR: A survey of HLLs, tools, andCompilers used for translating high level representation to hardware description language is presented and technical analysis of such tools and compilers is discussed as well.