H
Hideaki Arima
Researcher at Mitsubishi
Publications - 43
Citations - 896
Hideaki Arima is an academic researcher from Mitsubishi. The author has contributed to research in topics: Layer (electronics) & Capacitor. The author has an hindex of 17, co-authored 43 publications receiving 896 citations. Previous affiliations of Hideaki Arima include Renesas Electronics.
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Patent
Multi-layered interconnection structure for a semiconductor device
Natsuo Ajika,Hideaki Arima +1 more
TL;DR: In this paper, the authors present an interconnection layer of a semiconductor device with a multi-layer structure formed from the bottom, of a refractory metal silicide layer, a first refractor metal nitride layer, and a second refractoric metal nitric layer.
Patent
Electrically programmable non-volatile memory device and manufacturing method thereof
TL;DR: In this article, a 1-transistor type flash EEPROM is described, which includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode.
Patent
Multi-layered interconnection structure for a semiconductor device and manufactured method thereof
Natsuo Ajika,Hideaki Arima +1 more
TL;DR: In this article, the authors present an interconnection layer of a semiconductor device with a multi-layer structure formed from the bottom, of a refractory metal silicide layer, a first refractor metal nitride layer, and a secondary refractoric metal nitriding layer.
Proceedings ArticleDOI
A 5 volt only 16M bit flash EEPROM cell with a simple stacked gate structure
TL;DR: In this article, a simple stacked gate structure and a conventional 06 mu m CMOS process was used to obtain a 36 mu m/sup 2/5 V only 16 Mb flash EEPROM cell.
Journal ArticleDOI
A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories
Yoshikazu Miyawaki,Takeshi Nakayama,Shinichi Kobayashi,Natsuo Ajika,Makoto Ohi,Yasushi Terada,Hideaki Arima,T. Yoshihara +7 more
TL;DR: To improve the performance of high-density flash memories, several circuit technologies have been developed and a word-line boost and clamp scheme realizes low supply voltage read operations and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations.