Showing papers in "IEEE Journal of Solid-state Circuits in 1992"

Low-power CMOS digital design

Abstract: Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >

A CMOS transconductance-C filter technique for very high frequencies

Abstract: CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters can be made. This integrator has good linearity properties and nondominant poles in the gigahertz range owing to the absence of internal nodes. The integrator has a tunable DC gain, resulting in a controllable integrator quality factor. Experimental results of a VHF CMOS transconductance-C low-pass filter realized in a 3- mu m CMOS process are given. Both the cutoff frequency and the quality factors can be tuned. The cutoff frequency was tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response of the passive prototype filter. Furthermore, a novel circuit for automatically tuning the quality factors of integrated filters built with these transconductors is described. >

A 10-b 20-Msample/s analog-to-digital converter

Abstract: A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9- mu m CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm/sup 2/ and dissipates 240 mW. >

Design techniques for high-speed, high-resolution comparators

Abstract: Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 mu V at a 10-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 mu V at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW. >

A high-speed CMOS comparator with 8-b resolution

Abstract: A comparator consisting of a differential input stage, two regenerative flip-flops, and an S-R latch is presented. No offset cancellation is exploited, which reduces the power consumption as well as the die area and increases the comparison speed. An experimental version of the comparator has been integrated in a standard double-poly double-metal 1.5- mu m n-well process with a die area of only 140*100 mu m/sup 2/. This circuit, operating under a +2.5/-2.5-V power supply, performs comparison to a precision of 8 b with a symmetrical input dynamic range of 2.5 V (therefore +or-0.5 LSB resolution is equal to +or-4.9 mV). >

A new design of the CMOS full adder

Abstract: By using the transmission function theory, two CMOS full adders are designed, both of which have simpler circuits than the conventional full adder. Computer simulations with SPICE2G5 show that they can realize the expected logic functions and they have desirable transfer characteristics. >

Digital-domain calibration of multistep analog-to-digital converters

Abstract: A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >

A CMOS 13-b cyclic RSD A/D converter

Abstract: A 13-b CMOS cyclic A/D converter that does not need trimming nor digital calibration is presented. The effects associated with the error on the gain factor 2 as well as the offset errors are corrected by taking full advantage of the redundant signed digit (RSD) principle. The gain error resulting from mismatches among switched capacitors is corrected by a novel strategy that implements an exact multiplication by four after two cycles. As a result, offset errors do not affect the integral or the differential linearities from the RSD algorithm. The remaining overall shift caused by offsets is reduced under the LSB level by a proper choice of capacitor switching sequence. The converter achieves 1/2 LSB integral and differential linearity at 25 kS/s; harmonic distortion is less than -83 dB. Chip area is 2.9 mm2 in a standard CMOS 3-mu-m technology, including control logic and the serial-to-parallel output shift register. Power consumption is 45 mW under +/-5-V supplies.

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

Abstract: An experimental 4-Mb flash EEPROM has been developed based on 0.6- mu m triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0*1.8 mu m/sup 2/ has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11*6.95 mm/sup 2/, and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm/sup 2/ by using the minimal cell size (2.0*10 mu m/sup 2/). >

Synthesis of control circuits in folded pipelined DSP architectures

Abstract: A systematic folding transformation technique to fold any arbitrary signal processing algorithm data-flow graph to a hardware data-flow architecture, for a specified folding set and specified technology constraints, is presented. The folding set specifies the processor and the time partition at which the task is executed and is typically obtained by performing scheduling and resource allocation for the algorithm data-flow graph and the specified iteration period. The constraints imposed on the hardware architecture are also assumed to be known. The technique is used to derive the control circuitry of the hardware architecture. The authors derive conditions for the validity of a specified folding set, and present approaches to generate the dedicated architecture using systematic folding of tasks to operators. They propose automatic retiming and pipelining of algorithms described by data-flow graphs for folding. The folding algorithm is applied after preprocessing the data-flow graph for automated pipelining and retiming. >

Statistical modeling of device mismatch for analog MOS integrated circuits

Abstract: A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms. >

A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths

Abstract: A field-programmable multiprocessor integrated circuit, PADDI (programmable arithmetic devices for high-speed digital signal processing), has been designed for the rapid prototyping of high-speed data paths typical to real-time digital signal processing applications. The processor architecture addresses the key requirements of these data paths: (a) fast, concurrently operating, multiple arithmetic units, (b) conflict-free data routing, (c) moderate hardware multiplexing (of the arithmetic units), (d) minimal branch penalty between loop iterations, (e) wide instruction bandwidth, and (f) wide I/O bandwidth. The initial version contains eight processors connected via a dynamically controlled crossbar switch, and has a die size of 8.9*9.5 mm in a 1.2- mu m CMOS technology. With a maximum clock rate of 25 MHz, it can support a computation rate of 200 MIPS and can sustain a data I/O bandwidth of 400 Mbytes/s with a typical power consumption of 0.45 W. An assembler and simulator have been developed to facilitate programming and testing of the chip. >

An implantable CMOS circuit interface for multiplexed microelectrode recording arrays

Abstract: A second-generation multichannel probe designed for measuring single-unit activity in neural structures is described. The probe includes CMOS circuitry for electronically positioning the recording sites with respect to the active neurons and for amplifying and multiplexing the recorded signals. The probe selects eight active recording sites from among 32 on the probe shank using a static input channel selector. The neural signals on the selected channels are then amplified and multiplexed to the outside world. The probe offers a typical AC gain of 300 (15 Hz to 7 kHz), a DC gain of 0.3, and an equivalent input noise of 15 mu V rms. Operating from a single 5-V supply, the probe dissipates 2.5 mW of power and implements channel selection, self-testing, data output, and initialization using three external leads. The probe is realized using 12 masks in a high-yield single-sided dissolved wafer process with a 3- mu m feature size for the circuitry and a 3- mu m pitch on the electrode shanks. >

A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s

Abstract: A phase and frequency detector IC is presented that operates up to an NRZ bit rate of 8 Gb/s. The IC comprises a phase detector (PD), a quadrature phase detector (QPD), and frequency detector (FD). In the PD and QPD the VCO signal and the quadrature VCO signal are sampled by the NRZ input signal. The two beat notes provided by this operation are subsequently processed in the FD. The superposition of the FD output and the PD output signals are then fed into a passive loop filter (lag/lead filter). The loop filter and the VCO are external components. The measured pull-in range is >+or-100 MHz at 8 Gb/s. The measured r.m.s. time jitter of the extracted clock is less than 1.9 ps for a pseudorandom bit sequence (PRBS) length of 2/sup 23/-1. A 0.9- mu m 12-GHz f/sub T/ silicon bipolar process was used to fabricate the chip with a total power consumption of 1.4 W. >

A 100-MHz 2-D discrete cosine transform core processor

Abstract: A 100-MHz two-dimensional discrete cosine transform (DCT) core processor applicable to the real-time processing of HDTV signals is described. An excellent architecture utilizing a fast DCT algorithm and multiplier accumulators based on distributed arithmetic have contributed to reducing the hardware amount and to enhancing the speed performance. A layout scheme with a column-interleaved memory and a new ROM circuit are introduced for the efficient implementation of memory-based signal processing circuits. Furthermore, mean values of errors generated in the core were minimized to enhance the computational accuracy with the word-length constraints. Consequently, it features the fastest operating speed and the smallest area with sufficient accuracy to satisfy the specifications in CCITT recommendation H.261. The core integrates about 102 K transistors and occupies 21 mm/sup 2/ using 0.8- mu m double-metal CMOS technology. >

Improved implementation of the silicon cochlea

Abstract: The original 'Analog electronic cochlea' of R.F. Lyon and C.A. Mead (Trans. Acoust., Speech, Signal Processing, vol.36, no.7, p.1119-34, 1988) used a cascade of second-order filter sections in subthreshold analog VLSI to implement a low-power, real-time model of early auditory processing. Experience with many silicon-cochlea chips has allowed the identification of a number of important design issues, namely dynamic range, stability, device mismatch, and compactness. In this, paper, the original design is discussed in light of these issues, and circuit and layout techniques are described which significantly improve its performance, robustness, and efficiency. Measurements from test chips verify the improved performance. >

A reconfigurable VLSI neural network

Abstract: Due to the variety of architectures that need be considered while attempting solutions to various problems using neural networks, the implementation of a neural network with programmable topology and programmable weights has been undertaken. A new circuit block, the distributed neuron-synapse, has been used to implement a 1024 synapse reconfigurable network on a VLSI chip. In order to evaluate the performance of the VLSI chip, a complete test setup consisting of hardware for configuring the chip, programming the synaptic weights, presenting analog input vectors to the chip, and recording the outputs of the chip, has been built. Following the performance verification of each circuit block on the chip, various sample problems were solved. In each of the problems the synaptic weights were determined by training the neural network using a gradient-based learning algorithm which is incorporated in the experimental test setup. The results of this work indicate that reconfigurable neural networks built using distributed neuron synapses can be used to solve various problems efficiently. >

Fully bipolar, 120-Msample/s 10-b track-and-hold circuit

Abstract: Describes the design and experimental results of a fully bipolar track-and-hold (T&H) circuit for use in video applications. A fully differential, open-loop approach has been chosen in order to meet the specifications with respect to track-to-hold step, droop rate, and hold-mode feedthrough. In order to obtain maximum high-frequency performance, p-n-p transistors have been omitted from the design. The T&H circuit has been realized in a 3-GHz f/sub T/ bipolar production process with a minimum emitter size of 2*9 mu m/sup 2/. The die size is 0.25 mm/sup 2/, consuming 40 mW from a single 5-V power supply. Ten-bit performance has been measured up to 12-Msample/s full-Nyquist sampling rate. At 200 Msample/2, 8-b performance has been observed over the full-Nyquist band. >

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning

Abstract: A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V/sub p-p/). The complete system operates with supply voltages of +or-2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5- mu m n-well CMOS process. >

GANGLION-a fast field-programmable gate array implementation of a connectionist classifier

Abstract: 71 The architecture, implementation, and application of GANGLION, a totally digital connectionist classifier, are described. This fully interconnected feedforward net with one hidden layer is capable of generating 4.48 billion interconnection/s. The architecture is realized on a single 9U VME card and is built entirely from off-the-shelf components. The very high throughput of 20 million decision/s is achieved by making efficient use of field-programmable gate arrays. Specifically, the authors take advantage of the reprogrammability of the devices to automatically generate new custom hardware for each application of the classifier. >

Digitally adjustable resistors in CMOS for high-performance applications

Abstract: Methods by which CMOS circuits can be adjusted digitally to generate controlled impedances for use in high-performance circuits are described. Since digital signals are the only inputs to these circuits, on-chip DC power dissipation can be reduced, the circuit can be made more robust, and the impedance of the circuit can be adjusted by manipulating the input digital information. A design of a CMOS series terminated line driver is discussed, and the utilization of the controlled impedance in terminating transmission lines on-chip, constant delay lines, and controlled di/dt output buffers is discussed. >

A 54*54-b regularly structured tree multiplier

Abstract: A 54-b*54-b parallel multiplier was implemented in 0.88- mu m CMOS using the new, regularly structured tree (RST) design approach. The circuit is basically a Wallace tree, but the tree and the set of partial-product-bit generators are combined into a recurring block which generates seven partial-product bits and compresses them to a pair of bits for the sum and carry signals. This block is used repeatedly to construct an RST block in which even wiring among blocks included in wire shifters is designed as recurring units. By using recurring wire shifters, the authors can expand the level of repeated blocks to cover the entire adder tree, which simplifies the complicated Wallace tree wiring scheme. In addition, to design time savings, layout density is increased by 70% to 6400 transistors/mm/sup 2/, and the multiplication time is decreased by 30% to 13 ns. >

An analytical access time model for on-chip cache memories

Abstract: An analytical access time model for on-chip cache memories that shows the dependence of the cache access time on the cache parameters is described. The model includes general cache parameters, such as cache size (C), block size (B), and associativity (A), and array configuration parameters that are responsible for determining the subarray aspect ratio and the number of subarrays. With this model, a large cache design space can be covered, which cannot be done using only SPICE circuit simulation within a limited time. Using the model, it is shown that for given C, B, and A, optimum array configuration parameters can be used to minimize the access time; if the optimum array parameters are used, then the optimum access time is roughly proportional to the log (cache size), and when the optimum array parameters are used, larger block size gives smaller access time, but larger associativity does not give smaller access time because of the increase of the data-bus capacitances. >

Start-up and frequency stability in high-frequency oscillators

Abstract: Start-up criteria in harmonic oscillators are explored. Conventional criteria for start-up prediction are shown to be necessary but not always sufficient for high-frequency oscillators, due to the effects of parasitic elements. Design methods are derived to allow design of reliable oscillators with a well-defined frequency of oscillation. The theory is confirmed with the design, fabrication, and characterization of a 2-GHz monolithic LC oscillator. >

High-linearity continuous-time filter in 5-V VLSI CMOS

Abstract: High-linearity self-tuning continuous-time filters, fabricated in a standard 1.6- mu m 5-V CMOS process, are presented. Frequency control is achieved using switchable arrays of highly linear double-polysilicon capacitors in an active RC filter structure, resulting in tunable filters with very low signal distortion. One filter, a Tow-Thomas biquad, exhibits dynamic range and signal linearity of typically 91 dB. Another smaller implementation, a Sallen and Key filter, attains >or=76 dB. Cutoff frequency response is maintained to an accuracy of around +or-5%. >

Built-in current testing

Abstract: Built-in current (BIC) testing has proven to be useful through a number of IC fabrication experiments. In this paper the experience gained from these experiments is summarized. >

A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier

Abstract: A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power. >

Tunable BiCMOS continuous-time filter for high-frequency applications

Abstract: A BiCMOS fully differential transconductor based on MOS transistors operating in the linear region is presented. The circuit has an equivalent nondominant pole located above 1.5 GHz. This makes it suitable for high-frequency continuous-time filters. A second-order low-pass filter using the new transconductor realized in a 2- mu m BiCMOS technology is reported. The cutoff frequency f/sub 0/ of the cell is tunable in the range of 8-32 MHz and the quality factor is 2. The filter THD stays lower than -40 dB for an output signal up to 3.2 V/sub p-p/ at 5-MHz frequency. The area of the cell is 0.322 mm/sup 2/ and the power consumption (with f/sub 0/=25 MHz) is 30 mW with a single 5-V power supply. >

Design of a bipolar 10-MHz programmable continuous-time 0.05 degrees equiripple linear phase filter

Abstract: A bipolar seventh-order 0.05 degrees equiripple linear phase (constant group delay) transconductance-capacitor (g/sub m/-C) low-pass filter with a cutoff frequency (f/sub c/) tunable between 2 and 10 MHz is presented. Programmable equalization up to 9 dB at f/sub c/ is also provided. Total harmonic distortion at 2 V/sub p-p/ is less than 1%, with a dynamic range equal to 49 dB. Nominal power consumption from a single 5-V supply is 135 mW. The circuit also has a low-power mode ( >

The effect of logic block architecture on FPGA performance

Abstract: This authors explore the effect of logic block architecture on the speed of a field-programmable gate array (FPGA). Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each of a set of benchmark logic circuits is synthesized into FPGAs that use different logic blocks. The speed of the resulting FPGA implementations using each logic block is measured. While the results depend on the delay of the programmable routing, experiments indicate that five- and six-input lookup tables and certain multiplexer configurations produce the lowest total delay over realistic values of routing delay. The fine grain blocks, such as the two-input NAND gate, exhibit poor performance because these gates require many levels of logic block to implement the circuits and hence require a large routing delay. >