A method of fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12), forming on the surface (12) of the silicon substrate (10), by atomic layer deposition (ALD), a seed layer (20;20') characterised by a silicate material and forming, by atomic layer deposition (ALD) one or more layers of a high dielectric constant oxide (40) on the seed layer (20;20').

Method for fabricating a semiconductor structure including a metal oxide interface with silicon

PROBLEM TO BE SOLVED: To provide a method for manufacturing a polarizing plate which is capable of uniformly pressurizing a laminate (a polarizing film and a transparent film) constituting a polarizing plate even if using sticking rolls of which the diameter is relatively smaller, and an apparatus for manufacturing a polarizing plate.SOLUTION: A method for manufacturing a polarizing plate includes: an adhesive coating process for applying an active energy ray curable adhesive to one surface of a transparent film or to one surface or both surfaces of a polarizing film; a sticking process for sticking the transparent film and the polarizing film by pressing at least one of a pair of sticking rolls toward a direction of the other sticking roll by using at least one pressing roll provided in contact with the sticking rolls in a state where a laminate formed by laminating the transparent film on one surface or both surfaces of the polarizing film via the adhesive is interposed between the pair of sticking rolls rotating in a conveyance direction; and an active energy ray irradiation process for curing the adhesive by irradiating the laminate with the active energy ray. A diameter of the center part of the pressing roll is larger than a diameter of the center part of the sticking rolls in contact with the pressing roll.

Method for manufacturing polarizing plate

Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.

Hybrid built-in self test (bist) architecture for embedded memory arrays and an associated method

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same

Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

Remote bist for high speed test and redundancy calculation

PROBLEM TO BE SOLVED: To efficiently control a power system by utilizing the capability of a secondary battery. SOLUTION: An apparatus 30 for power system control uses a secondary battery provided on a customer side for consuming power, connected to a power system for supplying power to the customer, and charged and discharged for a benefit of the customer. The apparatus comprises: a control variable calculating part 311 that calculates a total of charging/discharging quantity by all secondary batteries necessary for controlling the power system; an effect calculating part 314 that calculates the sensitivity of each secondary battery to the power system of each secondary battery as control effects of the secondary batteries to the power system; and a distribution quantity calculating part 313 that performs distribution calculation for distributing the total charging/discharging quantities calculated by the control variable calculating part 311 to each secondary battery in descending order of magnitudes of the control effects calculated by the effect calculating part 314. Each secondary battery is controlled based on the result of the distribution calculation by the distribution quantity calculating part 313. COPYRIGHT: (C)2010,JPO&INPIT

Power system control method and power system controller using secondary battery

PROBLEM TO BE SOLVED: To improve durability of a polarizing plate formed by laminating a cycloolefin based resin film on one surface of a polarizing film consisting of a polyvinyl alcohol based resin via an adhesive layer and laminating a cellulose based resin film on the other surface via an adhesive layer, respectively, and to provide an advantageous manufacturing method of the polarizing plate. SOLUTION: The polarizing plate is made by laminating the cycloolefin based resin film on one surface of the polarizing film consisting of the polyvinyl alcohol based resin via an adhesive layer and laminating the cellulose based resin film on the other surface via an adhesive layer, and the polarizing plate is provided, of which the outer peripheral edge part is formed in an unexposed state of the polarizing film. The method for manufacturing the polarizing plate is also provided, in which after chip-cutting the polarizing plate in the laminated state as the above, advantageously, in the state in which the adhesive layer is formed at least on one outside thereof, especially, outside the cycloolefin based resin film layer, the polarizing plate is manufactured by performing cutting work of the outer peripheral edge part. COPYRIGHT: (C)2006,JPO&NCIPI

Polarizing plate and manufacturing method therefor

An optical pick-up head of the present invention includes a semiconductor substrate, a semiconductor laser mounted on the semiconductor substrate, a first photodetector for receiving a laser beam emitted from the semiconductor laser and reflected from an optical storage medium and outputting a current signal in accordance with the light amount of the received laser beam, and a current-voltage conversion circuit for converting the current signal to a voltage signal. The semiconductor laser is supplied with a high-frequency signal for preventing an output from fluctuating due to the laser beam reflected from the optical storage medium, and the photodetector and the current-voltage conversion circuit are formed on the semiconductor substrate.

Optical pick-up head and information recording/reproducing apparatus

[PROBLEMS] To provide an optical film laminate having a thin thickness, excellent durability and excellent productivity and a display device using the laminate. [MEANS FOR SOLVING PROBLEMS] Disclosed is an optical film laminate comprising a linear polarizing plate having a protective film on at least one surface and a retardation film laminated on the linear polarizing plate through an adhesive layer, wherein the adhesive layer comprises a curable adhesive agent which has a volatile matter content of less than 8% by weight when heated at 100°C under ambient pressure for 10 minutes before curing. The linear polarizing plate preferably has the protective film on one surface and the adhesive layer on the surface opposed to the protective film. The adhesive agent is preferably a thermosetting or active-energy-ray-curable adhesive agent which comprises a compound having at least one (meth)acryloyl group in the molecule, more preferably an adhesive agent which has a temperature at which the tensile loss factor (tanδ) reaches its maximum upon curing of 0°C or higher in the dynamic mechanical property measurement (measured at a frequency of 1 Hz). The laminate can be used as a component for an image display device such as a liquid crystal display device, an organic electroluminescence display device and a touch panel.

Optical film laminate and display device using the same

A semiconductor integrated circuit device includes a test circuit including a first latch circuit for holding a test pattern input to an electronic circuit operating in accordance with a clock signal and a second latch circuit for holding the output signal of the electronic circuit corresponding to the test pattern. In the test circuit, the clock signal having a frequency higher than the noise frequency generated in the power line at the time of starting to supply the clock signal to the electronic circuit is continuously supplied to the electronic circuit and the test circuit, while at the same time performing, in accordance with the clock signal in a period longer than the period of the clock signal, the operation of inputting the test pattern to the first latch circuit and the operation of outputting the output signal held in the second latch circuit.

Hideki Hayashi

Papers

Power system control method and power system controller using secondary battery

Polarizing plate and manufacturing method therefor

Optical pick-up head and information recording/reproducing apparatus

Optical film laminate and display device using the same

Semiconductor integrated circuit device and method of testing it