Keiichi Higeta

TL;DR: Key techniques for achieving this speed are a decoder using source-coupled-logic circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array.

TL;DR: In this article, a new capacitor technology, with extremely thin Ta 2 O 5 film deposition and weak-spot oxidation, was developed to realize high capacitance and high reliability, with a capacitance of 85 fF/µm2.

TL;DR: In this paper, a memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit blocks are formed in different areas and the second logic circuits is located between a pair of memory blocks.

TL;DR: In this article, the authors propose a first variable delay circuit which delays a timing signal for activating a sense amplifier, which is supplied with a signal read out from a memory array and amplifies the signal so that a timing difference between a dummy signal read from a dummy memory cell and the timing signal of the sense amplifier is detected by a detection circuit to be made small in accordance with an output of the detection circuit.

TL;DR: A 25Gb/s transceiver equalizing over 50dB channel loss is targeted, and a sub-mV dynamic DC offset cancelation and a decision-feedback equalizer (DFE) with a bias-controlled tap slicer are adopted to improve on the minimum input sensitivity and enable data transmission through a channel with over 50 dB loss.