The author presents a new technique, the don't-care propagation method, for logic verification and design error location in a circuit. Test patterns for single stuck-line faults are used to compare the gate-level implementation of a circuit with its functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistency that may exist between the specification and the implementation. This technique can determine the region containing the error. It has very high resolution and reduces the debugging time by the designers. Extensive experimental results were obtained to demonstrate the effectiveness of the new approach. >

Locating logic design errors via test generation and don't-care propagation

In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistencies that may exist between the functional-level description and its gate-level implementation. In this paper we present a method that determines the areas, within the gate-level circuit, that contain the functional errors. The indicated areas are shown to have sufficient resolution to allow the designer to quickly find the cause of the inconsistency and, therefore, reduce the time required for debugging.

Locating Functional Errors in Logic Circuits

The PowerPC logic verification methodology is a general purpose approach suitable for a large class of chip designs that can exceed five million transistors in size. Several validation techniques are integrated into an automated logic verification strategy. The success of this methodology has been demonstrated by realizing three PowerPC microprocessor chips that were functional the first time.

Logic Verification Methodology for PowerPC&#8482; Microprocessors

A technology mapping system, used for computer design in NEC, is presented. The features of this system are technology conversion and logical/physical optimization, based on a rule base, partitioning support, conversion verification and special layout consideration. This system is practically used for many applications for technology mapping, including redesigning an existing total unit into a new unit, based on up-to-date LSI technology. The resulting effect is quick inputting of integrated circuit technology progress into practical computer design area.

TRIP: An Automated Technology Mapping System

An integrated design system using CAD tools, which was applied to the design of the supercomputer (SX-1, SX-2), is described. The key points for designing the large system are a short design cycle, high productivity, high quality and user-friendly interface to the CAD system. Three strategies have been adopted: engineering work station utilization, thorough verification in an early design stage and establishment of a design flow using CAD tools. By the CAD system based on those strategies, a supercomputer with high quality was successfully designed in a short time.

Integrated Design System for Supercomputer SX-1/SX-2

Logic verification using automated test generation and simulation is described, in which functional design and structural design results are compared for functional equivalence. This new approach has been developed as a function of a mixed level simulator, MIXS1, and has strengthened MIXS top-down and bottom-up design support capabilities.

Hidetoshi Tanaka

Papers

Logic design verification using automated test generation