Open AccessProceedings Article
Logic design verification using automated test generation
Tohru Sasaki,Shunichi Kato,Nobuyoshi Nomizu,Hidetoshi Tanaka +3 more
- pp 88-94
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TLDR
Logic verification using automated test generation and simulation is described, in which functional design and structural design results are compared for functional equivalence.Abstract:
Logic verification using automated test generation and simulation is described, in which functional design and structural design results are compared for functional equivalence. This new approach has been developed as a function of a mixed level simulator, MIXS1, and has strengthened MIXS top-down and bottom-up design support capabilities.read more
Citations
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Proceedings ArticleDOI
Locating logic design errors via test generation and don't-care propagation
TL;DR: The author presents a new technique, the don't-care propagation method, for logic verification and design error location in a circuit that has very high resolution and reduces the debugging time by the designers.
Proceedings ArticleDOI
Locating Functional Errors in Logic Circuits
TL;DR: A method is presented that determines the areas, within the gate-level circuit, that contain the functional errors and is shown to have sufficient resolution to allow the designer to quickly find the cause of the inconsistency and, therefore, reduce the time required for debugging.
Proceedings ArticleDOI
Logic Verification Methodology for PowerPC™ Microprocessors
Charles H. Malley,Max Dieudonné +1 more
TL;DR: The PowerPC logic verification methodology is a general purpose approach suitable for a large class of chip designs that can exceed five million transistors in size and has been demonstrated by realizing three PowerPC microprocessor chips that were functional the first time.
Proceedings ArticleDOI
TRIP: An Automated Technology Mapping System
TL;DR: A technology mapping system, used for computer design in NEC, is presented, which is practically used for many applications for technology mapping, including redesigning an existing total unit into a new unit, based on up-to-date LSI technology.
Proceedings ArticleDOI
Integrated Design System for Supercomputer SX-1/SX-2
TL;DR: An integrated design system using CAD tools, which was applied to the design of the supercomputer (SX-1, SX-2), is described, and a supercomputer with high quality was successfully designed in a short time.
References
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Journal ArticleDOI
Boolean comparison of hardware and flowcharts
TL;DR: The Boolean comparison technique was used on the IBM 3081 project to establish that hardware flowcharts and the detailed hardware logic design were functionally equivalent.
Proceedings ArticleDOI
MIXS: A Mixed Level Simulator for Large Digital System Logic Verification
TL;DR: A mixed level simulator, MIXS, is a logic verification tool which has multiple simulation capabilities and techniques are time wheel and selective trace algorithm for functional level simulation based on 'node' model concept and the linkage function of functional models.
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