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Nobuyoshi Nomizu
Researcher at NEC
Publications - 11
Citations - 135
Nobuyoshi Nomizu is an academic researcher from NEC. The author has contributed to research in topics: Logic simulation & Register-transfer level. The author has an hindex of 5, co-authored 11 publications receiving 135 citations.
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Patent
Hardware logic simulator
TL;DR: In this paper, a hardware logic simulator includes a first memory, having memory locations respectively corresponding to a plurality of signals in a logic circuit to be simulated, for storing data representing states of the plurality of signal, and a second memory having memory location corresponding to those of the first memory and an address bus common therewith.
Patent
Logic simulator using small capacity memories for storing logic states, connection patterns, and logic functions
Nobuyoshi Nomizu,Tohru Sasaki +1 more
TL;DR: In this paper, a logic simulator for simulating operation of a logic circuit is provided with gates divisible into successive levels according to a connection pattern between the gates, where a pattern memory memorizes the connection pattern as a bit sequence representative of direct connections between each gate of each level to the gates of a preceding level.
Proceedings ArticleDOI
MIXS: A Mixed Level Simulator for Large Digital System Logic Verification
TL;DR: A mixed level simulator, MIXS, is a logic verification tool which has multiple simulation capabilities and techniques are time wheel and selective trace algorithm for functional level simulation based on 'node' model concept and the linkage function of functional models.
Proceedings ArticleDOI
HAL II: A Mixed Level Hardware Logic Simulation System
TL;DR: This paper describes a mixed level hardware logic simulation system, called HAL II, which can handle a maximum of 5.8 million gates and a high level design language FDL (Functional Description Language).
Proceedings Article
Logic design verification using automated test generation
TL;DR: Logic verification using automated test generation and simulation is described, in which functional design and structural design results are compared for functional equivalence.