Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic

Low power domino logic circuits in deep-submicron technology using CMOS

Real-time fault tolerant full adder design for critical applications

Critical role is played by multipliers in modern digital signal processing systems. The overall system is affected by multipliers in terms of speed and computational complexity. In this paper, a Han–Carlson adder (HCA) based high-speed Vedic multiplier is proposed. The proposed Vedic multiplier uses Urdhva–Tiryakbhyam sutra of Vedic multiplication. Han–Carlson adder is one of the parallel-prefix adders which provides high-speed to the proposed multiplier architecture. Proposed architecture of 64 × 64 bit Vedic multiplier is implemented using Xilinx ISE 14.2 navigator in VHDL. The implementation results of proposed architecture are compared with conventional Vedic multipliers with different adders which show that the conventional multipliers is having larger time delay as compared to proposed multiplier. Furthermore, complex multiplication architectures, using three and four 32 × 32 bit proposed Vedic multipliers are also implemented. The results of these complex multiplication architectures are also compared with conventional Booth multiplier and Array multiplier based architectures which show that the complex multiplication using proposed architecture provides improved delay, low hardware (LUTs) and low complexity.

Han–Carlson adder based high-speed Vedic multiplier for complex multiplication

This paper presents a design of 4-bit multiplier using full adder cell based on full swing gate diffusion input technique. The proposed adder design consists of 18 transistors and compared with different logic styles for full adders through cadence virtuoso simulation based on TSMC 65nm models at a supply voltage of 1v and frequency 250MHz. The simulation results showed that the proposed full adder design dissipates low power while improving the area and provides full swing output voltage among all the designs taken for comparison. The proposed full adder used to design Array, Barun and Baugh Wooley multipliers, Energy and Transistor count of these multipliers improved compared to CMOS.

Himanshu Lohani

Papers

Design, implementation and performance comparison of multiplier topologies in power-delay space