Mansi Jhamb

TL;DR: In this article, the implementation of an 8-bit multiplier design employing CMOS full adders, full adder using Double Pass Transistor (DPL) and multi-output carry Lookahead logic (CLA) is addressed.

TL;DR: A new iris recognition technique is proposed using (Scale Invariant Feature Transform) SIFT that is computationally effective as well as reliable in terms of recognition rates.

TL;DR: In this article, the authors present a qualitative and quantitative analysis of an asynchronous pipelined adder design with two latest computation completion sensing approaches based on Pseudo NMOS logic and other based on C-element.

TL;DR: A high level implementation of a micropipelined asynchronous architecture of L1 cache, comprising of data and instruction caches has a wide array of configurable parameters and has high average cache throughput and low latency.

TL;DR: This work exhaustively compares the latest version of comparators pertaining to the application of low-power, high-speed wearables using HSPICE environment at 90 nm process technology and finds that the critical path delay of the dynamic version turns out to be 17.63% less than static.