An RF-DC power conversion system is designed to efficiently convert far-field RF energy to DC voltages at very low received power and voltages. Passive rectifier circuits are designed in a 0.25 mum CMOS technology using floating gate transistors as rectifying diodes. The 36-stage rectifier can rectify input voltages as low as 50 mV with a voltage gain of 6.4 and operates with received power as low as 5.5 muW(22.6 dBm). Optimized for far field, the circuit operates at a distance of 44 m from a 4 W EIRP source. The high voltage range achieved at low load current make it ideal for use in passively powered sensor networks.

Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks

The idea of wireless power transfer (WPT) has been around since the inception of electricity. In the late 19th century, Nikola Tesla described the freedom to transfer energy between two points without the need for a physical connection to a power source as an ?all-surpassing importance to man? [1]. A truly wireless device, capable of being remotely powered, not only allows the obvious freedom of movement but also enables devices to be more compact by removing the necessity of a large battery. Applications could leverage this reduction in size and weight to increase the feasibility of concepts such as paper-thin, flexible displays [2], contact-lens-based augmented reality [3], and smart dust [4], among traditional point-to-point power transfer applications. While several methods of wireless power have been introduced since Tesla?s work, including near-field magnetic resonance and inductive coupling, laser-based optical power transmission, and far-field RF/microwave energy transmission, only RF/microwave and laser-based systems are truly long-range methods. While optical power transmission certainly has merit, its mechanisms are outside of the scope of this article and will not be discussed.

Harvesting Wireless Power: Survey of Energy-Harvester Conversion Efficiency in Far-Field, Wireless Power Transfer Systems

A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

The vision of embedding connectivity into billions of everyday objects runs into the reality of existing communication technologies -- there is no existing wireless technology that can provide reliable and long-range communication at tens of microwatts of power as well as cost less than a dime While backscatter is low-power and low-cost, it is known to be limited to short ranges This paper overturns this conventional wisdom about backscatter and presents the first wide-area backscatter system Our design can successfully backscatter from any location between an RF source and receiver, separated by 475 m, while being compatible with commodity LoRa hardware Further, when our backscatter device is co-located with the RF source, the receiver can be as far as 28 km away We deploy our system in a 4,800 ft2 (446 m2) house spread across three floors, a 13,024 ft2 (1210 m2) office area covering 41 rooms, as well as a one-acre (4046 m2) vegetable farm and show that we can achieve reliable coverage, using only a single RF source and receiver We also build a contact lens prototype as well as a flexible epidermal patch device attached to the human skin We show that these devices can reliably backscatter data across a 3,328 ft2 (309 m2) room Finally, we present a design sketch of a LoRa backscatter IC that shows that it costs less than a dime at scale and consumes only 925 mW of power, which is more than 1000x lower power than LoRa radio chipsets

https://dl.acm.org/doi/pdf/10.1145/3130970

LoRa Backscatter: Enabling The Vision of Ubiquitous Connectivity

A passive UHF RF identification (RFID) tag IC with embedded 2-KB ferroelectric RAM (FeRAM) for rewritable applications enables a 2.9 times faster read-and-write transaction time over EEPROM-based tag ICs. The resulting FeRAM-based tag has a nominally identical communication range for both read and write operations, which is indispensable for data write applications. The evaluated tag communication range with a folded dipole antenna is from 0 m to 4.3 m, at the 953-MHz carrier frequency with 4-W transmitting Effective Isotropic Radiated Power (EIRP) from a reader/writer. The developed tag IC features two circuit blocks to maximize the communication range in 0.35-mum CMOS/FeRAM technology. First is a CMOS-only full-wave rectifier, which can improve the measured efficiency by up to 36.6% by reducing the input parasitic capacitances and optimization of multiplier structure. This efficiency is more than twice that of previously-published results. Second is a low-voltage current-mode ASK demodulator to accommodate a low-breakdown voltage of FeRAM, which converts the ASK power modulation into a linearly modulated current over an incoming power range of 27 dB, corresponding to the entire communication range. The developed demodulator can thus resolve the primary design tradeoff issue between device protection and detection sensitivity in the conventional voltage-mode demodulator

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35- $\mu{\hbox {m}}$ Technology

A passive UHF RFID tag LSI in 0.35mum CMOS with 2kb FeRAM enables the 2.9-times higher 32b read-and-write throughput over an EEPROM-based tag. A CMOS full-wave rectifier improves the power efficiency from 16.6% up to 36.6% by lossless internal Vth cancellation and mirror stack architecture. A current-mode ASK demodulator converts the 15% power modulation into linear current signal over a 27dB dynamic range of the incoming power

A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology

The recent rapid spread of smart-phone use has resulted in a strong demand for a multi-band RF part with reduced size and power consumption. In the creation of an ideal RF system-on-a-chip, the biggest challenge is to realize a fully integrated PA in CMOS. In conventional PAs in compound semiconductor technologies, face-up wire-bond assembly with off-chip matching components is typically used, but flip-chip packaging is more suitable for slim mobile phones in which low-profile components are desired as well as for future integration with an RF transceiver in which the same packaging scheme is widely used. The PA for GSM [1] was insufficient for our target, so we needed to greatly improve the linearity in order to comply with the W-CDMA standard, which has better frequency-usage efficiency. Conventional CMOS PAs only support a single band [2,3] or are for WLAN [4] where the output power level is low (typically about 20dBm). In this paper, we present a fully-integrated triple-band linear CMOS PA for W-CDMA. Its flip-chip package is just 3.5×4×0.7mm3, and the average current consumption is less than 20mA.

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets

An on-chip CMOS RF power detector (PD) is described that has internal temperature compensation and the highest reported linearity. The PD generates a DC current that is proportional to the square root of the RF input power by use of a new detection technique that utilizes p-n junction diodes. The generated DC current obtained by subtracting a replicated current produces the real-time temperature compensation. This subtraction method also suppresses the generated-current error caused by the parasitic element, thereby improving the linearity of the PD. The proposed on-chip PD was fabricated in 90-nm CMOS technology and integrated with a power amplifier (PA). The measured input range for a linearity error within ±0.5 dB was 27 dB at 0.824 GHz and 23 dB at 1.98 GHz. The measured results showed that the PD overcomes real-time temperature changes caused by self-heating, which depends on the output power of the PA. The PD consumes 0.3 mW at 0-dBm input power and occupies 0.04 mm2, which are small enough for the PA.

A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications

An interpolation circuit for generating interpolated and extrapolated differential voltages from first and second differential input voltages, comprises first (A) and second (B) differential amplifiers for inputting the first and second differential input voltages, respectively, and for generating a differential output voltage respectively between their inverted output terminal (AN, BN) and their respective non-inverted terminal (AP, BP). The interpolation circuit further comprises a first voltage dividing element array (NT1) disposed between the non-inverted output terminals (AP, BP) of the first and second differential amplifiers, and a second voltage dividing element array (NT2) disposed between the inverted output terminals (AN, BN) of the first and second differential amplifiers, so that the interpolated differential voltages are generated from nodes (n1, n2, n3) in the first voltage dividing element array (NT1) and nodes (n4, n5, n6) in the second voltage dividing element array (NT2). The interpolation circuit further comprises a third voltage dividing element array (NT1) disposed between the inverted output terminal (AN) of the first differential amplifier (A) and the non-inverted output terminal (BP) of the second differential amplifier (B), so that at least a pair of extrapolated differential voltages are generated from nodes (n10, n12) in the third voltage dividing element array (NT3).

Hiroyuki Nakamoto

Papers

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35- $\mu{\hbox {m}}$ Technology

A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets

A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications

Interpolation circuit having a conversion error correction range for higher-order bits and A/D conversion circuit utilizing the same