N
Naoyoshi Tamura
Researcher at Fujitsu
Publications - 69
Citations - 1003
Naoyoshi Tamura is an academic researcher from Fujitsu. The author has contributed to research in topics: Transistor & Silicon. The author has an hindex of 15, co-authored 69 publications receiving 995 citations.
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Patent
Semiconductor device and fabrication method thereof
TL;DR: In this article, a gate electrode is formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode.
Patent
Semiconductor device and production method thereof
TL;DR: In this article, a method of fabricating a semiconductor device that is able to suppress a short channel effect and improve carrier mobility is described. In this method, trenches are formed in a silicon substrate corresponding to a source region and a drain region, and the surfaces of the trenches are demarcated by facets.
Patent
P-channel MOS transistor, semiconductor integrated circuit device and fabrication process thereof
TL;DR: In this article, a p-channel MOS transistor includes source and drain regions of p-type formed in a silicon substrate at respective lateral sides of a gate electrode, where each of the sources and drains includes any of a metal film region and a metal compound film region as a compressive stress source accumulating therein.
Proceedings ArticleDOI
Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs
K. Goto,S. Satoh,Hiroyuki Ohta,S. Fukuta,T. Yamamoto,Toshihiko Mori,Y. Tagawa,T. Sakuma,Takashi Saiki,Y. Shimamune,Akira Katakami,Akiyoshi Hatada,Hiroshi Morioka,Y. Hayami,Satoshi Inagaki,Kazuo Kawamura,Y. S. Kim,H. Kokura,Naoyoshi Tamura,Naoto Horiguchi,M. Kojima,Toshihiro Sugii,K. Hashimoto +22 more
TL;DR: In this paper, a new process flow which selectively forms SELS only on the nMOS gate was developed to solve wafer bending problem, and a high performance 37nm gate n-MOSFET and 45nm gate pMOS-FET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A/A//spl m and 690/spl m/A-spl mm at V/sub dd/=1V/I/sub off/=100nA/m, respectively.
Patent
Semiconductor integrated circuit and fabrication process thereof
TL;DR: In this paper, a semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel mOS transistor constructed on a second device region on the silicon substrate.