Kazuaki Oishi

TL;DR: In this paper, a fractional N-frequency synthesizer includes an accumulator outputting an output value, and a spurious signal cancel circuit, consisting of a pulse forming circuit, a reset signal, and the output value of the accumulator, and outputting, in synchronism with the spurious signal cancelling reference signal, a pulse voltage signal having a pulse width proportional to the output values from a time when the reset signal is received.

TL;DR: In this article, a center frequency tuning technique for a second intermediate-frequency (IF) bandpass filter was proposed to guarantee the accuracy of the design, and a 450-kHz G/sub m/C band pass filter tuned using this technique has been developed to integrate the IF module for personal digital cellular (PDC) handsets for use in 0.35-/spl mu/m CMOS.

TL;DR: A fully-integrated triple-band linear CMOS PA for W-CDMA, which is more suitable for slim mobile phones in which low-profile components are desired as well as for future integration with an RF transceiver in which the same packaging scheme is widely used.

TL;DR: A fully integrated envelope elimination and restoration (EER) CMOS power amplifier (PA) has been developed for WCDMA and LTE handsets and was implemented in 90 nm CMOS technology.

TL;DR: In this article, a power supply device includes a linear regulator including an output stage amplifier, a current sensing circuit, and a switching regulator, which operate in collaboration with each other to generate an output voltage at an output node.