T
Tetsuo Matsuda
Researcher at Toshiba
Publications - 13
Citations - 528
Tetsuo Matsuda is an academic researcher from Toshiba. The author has contributed to research in topics: Layer (electronics) & Eddy current. The author has an hindex of 9, co-authored 13 publications receiving 528 citations. Previous affiliations of Tetsuo Matsuda include IBM.
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Patent
Method of manufacturing semiconductor devices
Tetsuo Matsuda,Haruo Okano +1 more
TL;DR: In this article, an improved method of manufacturing a semiconductor device was proposed, where an insulating film, a conducting film, and a refractory metal film are sequentially deposited on a substrate.
Patent
Eddy current loss measuring sensor, thickness measuring system, thickness measuring method, and recorded medium
TL;DR: In this article, the authors proposed a thickness measuring system consisting of an exciting coil for receiving high frequency current to excite a high frequency magnetic field, and a receiving coil for outputting the high-frequency current which is influenced by an eddy current loss caused by the current.
Patent
Semiconductor device manufacturing method and semiconductor device
Kazuyuki Higashi,Noriaki Matsunaga,Akihiro Kajita,Tetsuo Matsuda,Tadashi Iijima,Hisashi Kaneko,Hideki Shibata,Naofumi Nakamura,Minakshisundaran Balasubramanian Anand,Tadashi Matsuno,Katsuya Okumura +10 more
TL;DR: In this paper, a semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconducting substrate, and forming a lower level wiring in the trench, and then forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, and finally, a wiring trench in which at least the hard mask is exposed.
Patent
Fabrication process using a multi-layer antireflective layer
TL;DR: In this paper, a patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resists as a mask.
Patent
Fabrication process using a thin resist
TL;DR: In this paper, a patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resists as a mask.