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Holger Pirk

Researcher at Imperial College London

Publications -  35
Citations -  790

Holger Pirk is an academic researcher from Imperial College London. The author has contributed to research in topics: Cache & Data management. The author has an hindex of 11, co-authored 33 publications receiving 687 citations. Previous affiliations of Holger Pirk include Massachusetts Institute of Technology & IBM.

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Journal ArticleDOI

Hardware-oblivious parallelism for in-memory column-stores

TL;DR: This work proposes an alternative design for a parallel database engine, based on a single set of hardware-oblivious operators, which are compiled down to the actual hardware at runtime, which reduces the development overhead for parallel database engines, while achieving competitive performance to hand-tuned systems.
Patent

Cube faceted data analysis

TL;DR: In this paper, the authors present a method for displaying results of a search query in a search interface based on a facet hierarchy of documents that satisfy the query, and a cube structure based on the facet hierarchy and a multi-dimensional search interface.
Journal ArticleDOI

Voodoo - a vector algebra for portable database performance on modern hardware

TL;DR: This work uses Voodoo, a declarative intermediate algebra that abstracts the detailed architectural properties of the hardware, such as multi- or many-core architectures, caches and SIMD registers, without losing the ability to generate highly tuned code, to build an alternative backend for MonetDB, a popular open-source in-memory database.
Journal ArticleDOI

Evaluating end-to-end optimization for data analytics applications in weld

TL;DR: Using the optimizer designed, Weld accelerates data science workloads by up to 23X on one thread and 80X on eight threads, and its adaptive optimizations provide up to a 3.75X speedup over rule-based optimization.
Proceedings ArticleDOI

Database cracking: fancy scan, not poor man's sort!

TL;DR: An in-depth study of the reasons for the low CPU efficiency of pivoted partitioning is conducted and an optimized version with significantly higher (single-threaded) CPU efficiency is developed.