This paper presents a wideband low-noise amplifier (LNA) based on the cascode configuration with resistive feedback. Wideband input-impedance matching was achieved using a shunt-shunt feedback resistor in conjunction with a preceding π -match network, while the wideband gain response was obtained using a post-cascode inductor (LP), which was inserted between the output of the cascoding transistor and the input of the shunt-shunt resistive feedback network to enhance the gain and suppress noise. Theoretical analysis shows that the frequency response of the power gain, as well as the noise figure (NF), can be described by second-order functions with quality factors or damping ratios as parameters. Implemented in 90-nm CMOS technology, the die area of this wideband LNA is only 0.139 mm2 including testing pads. It dissipates 21.6-mW power and achieves S11 below -10 dB, S22 below -10 dB, flat S21 of 9.6 ±1.1 dB, and flat NF of 3.68 ± 0.72 dB over the 1.6-28-GHz band. Besides, excellent input third-order inter-modulation point of +4 dBm is also achieved. The analytical, simulated, and measured results are mutually consistent.

Analysis and Design of a 1.6–28-GHz Compact Wideband LNA in 90-nm CMOS Using a $ \pi $ -Match Input Network

A 90-nm CMOS low-noise amplifier (LNA) for 3-10-GHz ultra-wideband (UWB) applications is presented. The circuit adopts a single-ended dual-stage solution. The first stage is based on a current-reuse topology and performs UWB (3-10 GHz) input matching. The second stage is a cascode amplifier with resonant load to enhance gain and reverse isolation. Thanks to both the circuit solution and design approach, the LNA provides input matching, low noise, flat gain, and small group-delay variation in the UWB frequency range at minimum power consumption. The design is also conceived to cope with application issues such as low-cost off-chip interfaces and electrostatic discharge robustness. Measurements exhibit a 12.5-dB power gain in a 7.6-GHz 3-dB bandwidth, a minimum noise figure of 3 dB, a reverse isolation better than 45 dB up to 10.6 GHz, and a record small group-delay variation of ±12 ps. The LNA draws 6 mA from a 1.2-V power supply.

A 3–10-GHz Low-Power CMOS Low-Noise Amplifier for Ultra-Wideband Communication

A negative group delay (NGD) circuit has been employed to equalize a group delay variation in a broadband ultra-wideband (UWB) InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) amplifier. Using the NGD circuit, a part of a salient group delay characteristic in the operation band of broadband amplifiers can be suppressed without an increase of the entire group delay. The MMIC amplifier has a steep group delay increase in the lower frequency region of the full-band UWB band (3.1-10.6 GHz) due to the sum of phase variations near the cutoff frequencies of the HBTs. The NGD circuit has been inserted to reduce this increase of the group delay in the UWB band. By adding a three-cell NGD circuit while considering input and output matching at the input side of the MMIC amplifier, the group delay variation is decreased by 78%. However, gain was also decreased by insertion of the multistage NGD circuit. In an attempt to avoid this decrease in gain, a one-cell NGD circuit was inserted into the feedback loop of the MMIC amplifier, and as a result, we were able to decrease the group delay variation by 79%, with minimal gain deterioration.

Group Delay Equalized UWB InGaP/GaAs HBT MMIC Amplifier Using Negative Group Delay Circuits

A method is proposed to design wideband low-noise amplifiers (LNAs) made of cascaded common-gate (CG) and common-source (CS) stages with a parallel-to-series resonant interstage matching network. The first CG stage has a dual-band response, and the second CS stage has higher gain between these two bands. By applying the proposed interstage matching technique, conjugate matching is achieved at high and low bands, while the midband loss is compensated by the second stage. The output network of the first stage and the input network of the second stage resonate at the same frequency. Two wideband LNAs are designed based on this method and implemented in 0.18- μm RF-mixed signal CMOS process. The first LNA operates at 3.1-10.3 GHz, having 9.6-12.71 dB of power gain and 2.5-3.9 dB of noise figure (NF) at the power consumption of 13.4 mW. The second LNA operates at 14.3-29.3 GHz, having 8.25 ± 1.65 dB of power gain and 4.3-5.8 dB of NF at the power consumption of 13.9 mW.

http://cc.ee.ntu.edu.tw/~jfkiang/selected_publications/tmtt_2011_9.pdf

Design of Wideband LNAs Using Parallel-to-Series Resonant Matching Network Between Common-Gate and Common-Source Stages

This paper reports the design and analysis of 21-29-GHz CMOS low-noise amplifier (LNA), balun and mixer in a standard 0.18-μm CMOS process for ultra-wideband automotive radar systems. To verify the proposed LNA, balun, and mixer architectures, a simplified receiver front-end comprising an LNA, a double-balanced Gilbert-cell-based mixer, and two Marchand baluns was implemented. The wideband Marchand baluns can convert the single RF and local oscillator (LO) signals to nearly perfect differential signals over the 21-29-GHz band. The performance of the mixer is improved with the current-bleeding technique and a parallel resonant inductor at the differential outputs of the RF transconductance stage. Over the 21-29-GHz band, the receiver front-end exhibits excellent noise figure of 4.6±0.5 dB, conversion gain of 23.7±1.4 dB, RF port reflection coefficient lower than -8.8 dB, LO-IF isolation lower than -47 dB, LO-RF isolation lower than -55 dB, and RF-IF isolation lower than -35.5 dB. The circuit occupies a chip area of 1.25×1.06 mm2, including the test pads. The dc power dissipation is only 39.2 mW.

Design and Analysis of a 21–29-GHz Ultra-Wideband Receiver Front-End in 0.18- $\mu$ m CMOS Technology

A wideband low-noise amplifier (LNA) based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt-shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel RLC-branches, i.e., a second-order wideband bandpass filter. Besides, both the inductive series- and shunt-peaking techniques are used for bandwidth extension. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The CMOS ultra-wideband LNA dissipates 10.34-mW power and achieves S 11 below -8.6 dB, S 22 below -10 dB, S 12 below -26 dB, flat S 21 of 12.26 ± 0.63 dB, and flat NF of 4.24 ± 0.5 dB over the 3.1-10.6-GHz band of interest. Besides, good phase linearity property (group-delay variation is only ±22 ps across the whole band) is also achieved. The analytical, simulated, and measured results agree well with one another.

Analysis and Design of a CMOS UWB LNA With Dual- $RLC$ -Branch Wideband Input Matching Network

A 3.1-10.6-GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only plusmn16.7 ps across the whole band) using standard 0.13 mum CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 10.68 mW power and achieves input return loss (S11) of -17.5 ~ -33.6 dB, output return loss (S22) of -14.4 ~ -16.3 dB, flat forward gain (S21) of 7.92 plusmn 0.23 dB, and reverse isolation (S12) of -25.8 ~ -41.9 dB over the 3.1-10.6 GHz band of interest. State-of-the-art noise figure (NF) of 2.5 dB is achieved at 10.5 GHz. The measured 1-dB compression point (P1dB) and input third-order inter-modulation point (IIP3) were -14 dBm and -4 dBm, respectively, at 6 GHz.

A 2.5-dB NF 3.1–10.6-GHz CMOS UWB LNA with small group-delay-variation

A low-power-consumption 53-GHz (V-band) low-noise amplifier (LNA) using standard 0.13 mum CMOS technology is reported. To achieve sufficient gain, this LNA is composed of four cascaded common-source stages. Current-sharing technique is adopted in the third and the four stage to reduce the power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain at the design frequency. This LNA achieved voltage gain (Av) of 14 dB, very low noise figure (NF) of 6.13 dB, input referred 1-dB compression point (P1 dB-in) of -20 dBm, and input third-order inter-modulation point (IIP3) of -9 dBm at 53 GHz. It consumed only a very small dc power of 10.56 mW. In addition, the chip area was only 0.91times0.58 mm2, including all the test pads and bypass capacitors.

A low-power V-band CMOS low-noise amplifier using current-sharing technique

A low-power-consumption 53-GHz (V-band) low-noise amplifier (LNA) using standard 0.13 μm CMOS technology is reported. To achieve sufficient gain, this LNA is composed of four cascaded common-source stages. Current-sharing technique is adopted in the third and four stages to reduce the power dissipation. The output of each stage is loaded with an LC parallel resonance circuit to maximize the gain at the design frequency. This LNA achieved voltage gain (AV) of 14 dB, very low noise figure (NF) of 6.13 dB, input referred 1-dB compression point (P1dB-in) of −20 dBm, and input third-order inter-modulation point (IIP3) of −9 dBm at 53 GHz. It consumed only a very small dc power of 10.56 mW. In addition, the chip area was only 0.91 × 0.58 mm2, including all the test pads and bypass capacitors. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1876–1879, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23523

Hong-Yu Yang

Papers

Analysis and Design of a CMOS UWB LNA With Dual- $RLC$ -Branch Wideband Input Matching Network

A 2.5-dB NF 3.1–10.6-GHz CMOS UWB LNA with small group-delay-variation

A low-power V-band CMOS low-noise amplifier using current-sharing technique

A low-power V-band CMOS low-noise amplifier using current-sharing technique