We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mVp-p output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm 2 and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm 2 .

Area-efficient linear regulator with ultra-fast load regulation

A Hybrid-Mode LDO Regulator with Fast Transient Response Performance for IoT applications

Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator

This brief presents an NMOS-only voltage reference with small process variations for ultra-low-power applications. All MOSFETs work in the subthreshold region and are biased by the leakage current of the NMOS transistor manufactured in Deep-N-Well (DNW). By fitting the variations of threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula>) from slow/fast corners to typical corners linearly, an optimum body selection (OBS) is proposed to reduce the impact of the process variations from <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> or <inline-formula> <tex-math notation="LaTeX">$\Delta \text{V}_{\mathrm{ TH}}$ </tex-math></inline-formula> with the aid of the body effect. The proposed design was fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process, together with a baseline design without using the OBS. Based on the 25-chip measurement results, the output voltage variation of the proposed design is <inline-formula> <tex-math notation="LaTeX">$0.0035 \sigma /\mu $ </tex-math></inline-formula>, which is 61% smaller than that of the baseline design. Besides, for the proposed design with the OBS, the power consumption is 23pW (27°C), while the die area is 0.003mm2. The temperature coefficient is 52ppm/°C in a temperature range from 0°C to 85°C without trimming. The line sensitivity is 0.03%/V, and the power supply rejection ratio is 47dB at 100Hz.

A 23-pW NMOS-Only Voltage Reference With Optimum Body Selection for Process Compensation

A 134-nW Single BJT Bandgap Voltage and Current Reference in 0.18-µm CMOS

A Power-area-efficient output-capacitorless low- dropout (OCL-LDO) regulator with fast transient response is presented in this paper. The proposed technique permits the regulator to achieve small undershoot (overshoot) when the load steps up (down) and consumes little extra power. The proposed LDO regulator has been implemented and fabricated in a 0.18- μm CMOS process. It occupies an active area of0.0071mm2. The simulated results have shown that the proposed circuit consumes a quiescent current of 0.7 μΑ at no load, regulating the output at 0.7 V from a voltage supply of 0.9 V. The simulated transient output voltage is 47 mV when load current is stepped from 1 mA to 20 mA in 400 ns with C l =3D10 pF. Meanwhile, this circuit shows a good of flgure-of-merit (FOM).

An Area-Efficient Low Quiescent Current Output Capacitor-Less LDO with Fast Transient Response

This brief presents a picowatt CMOS voltage reference with ultra-low supply and wide temperature range. Biased by PMOS leakage current, ultra-low voltage and ultra-low power consumption are achieved. The temperature range is enlarged by using the increased bulk diode leakage current modulation (BDLCM) effect at high temperature. The proposed design is implemented in a standard 0.18- $\mu \text{m}$ CMOS process. The measurement results show that, the proposed circuit can provide an average voltage reference of 118.1 mV with a standard deviation of 1.3 mV. The minimum supply voltage is 250 mV and the line sensitivity (LS) is 0.3 %/V. The average temperature coefficient (TC) is 73.5 ppm/°C with a standard deviation of 11.7 ppm/°C within a temperature range from −40 °C to 140 °C. The power supply ripple rejection (PSRR) at 100 Hz is −65 dB. The power consumption at room temperature is 113 pW and the active area is 0.0009 mm2.

A −40 °C to 140 °C Picowatt CMOS Voltage Reference With 0.25-V Power Supply

In this paper, a fully-on-chip, NMOS low dropout voltage (LDO) regulator with a capacitance multiplier used for improving the stability and transient response is proposed. This compensation technology emulates a large capacitance value at the gate of the pass FET for high stability and fast transient response. The chip area is much reduced compared to a conventional design. The proposed LDO is designed in a 0.18-µm CMOS process and consumes 13.2 µA quiescent current with 0.1 V dropout and 1.0 V output voltages. It does not require any external compensation capacitor.

Chip-Area-Efficient Capacitor-less LDO Regulator with Fast-Transient Response

This paper presents a low power subthreshold CMOS voltage reference (CVR) with current loading capability. Based on the classical 2T CVR to achieve low temperature coefficient (TC), a sourcing PMOS is appropriately biased through a local negative feedback loop. Current loading capability is achieved without relying on an output buffer. The proposed CVR is designed in a standard 0.18-μm CMOS process. Simulation results show that the CVR is capable of delivering 300 μA while the generated Vref has less than 0.42% reduction. The minimum supply voltage is 0.5 V and typical power consumption is 3 nW. It achieves an average TC of 9 ppm/°C from -20 °C to 135 °C, line sensitivity of 0.069 %/v and power supply rejection of -65 dB@100Hz.

A Low-Power CMOS Voltage Reference with Current Loading Capability

The Internet of Things (loT) is developing rapidly, and energy harvesting (EH) provides the power source impetus for it. Still the energy collected from EH is generally underfed, which obliges EH powered modules to achieve low power consumption as much as possible. Hence, the growth of low voltage and low quiescent current designs are pushed forward. For applications with sub-10µA under low-supply (200-300mV), such as sensors for monitoring, SRAM [1], designing an additional regulator is overburdened and one solution is the voltage reference (VR) integrated with output buffer. Whereas the added buffer brings extra area and power consumption (e.g., microwatt), the mismatch substantially degrades the temperature coefficient (TC). Therefore, a sub-nanowatt VR with current sourcing capability is of momentous significance. Besides, supposing that the power consumption of the designed VR is in the order of picowatt, and due to the process restraint, the subsequent gates of MOS transistors connected to the VR output have leakage current of picoampere, it will directly cause the VR to be shut down, needless to mention the microampere loading capability. However, the existing CMOS voltage references (CVRs) hardly source current [2]–[6].

Hongchang Qiao

Papers

An Area-Efficient Low Quiescent Current Output Capacitor-Less LDO with Fast Transient Response

A −40 °C to 140 °C Picowatt CMOS Voltage Reference With 0.25-V Power Supply

Chip-Area-Efficient Capacitor-less LDO Regulator with Fast-Transient Response

A Low-Power CMOS Voltage Reference with Current Loading Capability

A 19-30ppm/°C Temperature Coefficient Sub-Nanowatt CMOS Voltage Reference with 10-µA Sourcing Capability