Quan Pan

TL;DR: A tri-loop LDO architecture is proposed and verified in a 65 nm CMOS process, where the output pole is set to be the dominant pole, and the internal poles are pushed to higher frequencies with only 50 μA of total quiescent current.

TL;DR: In this article, the authors presented a digitally controlled 1-V 30-Gb/s 1.37pJ/b optical receiver in 65-nm CMOS technology, which consists of an inverter-based inductive transimpedance amplifier, a fully integrated low-dropout regulator, a main amplifier and a two-stage limiting amplifier, and an output driver.

TL;DR: In this article, an 18-Gb/s fully integrated optoelectronic integrated circuit for short-distance communications is realized in the TSMC 65-nm CMOS process, which consists of a CMOS on-chip photodetector, an inverter-based cascode transimpedance amplifier, a DC offset cancellation buffer, a main amplifier, three-stage tunable continuous-time linear equalizer, a two-stage modified limiting amplifier, an adaptive equalization loop, a low dropout regulator, and a 50-Ω termination output buffer.

TL;DR: The proposed multiple-peaking scheme incorporates an input bond-wire and two on-chip inductors to mitigate the photodetector capacitive loading, achieving an overall bandwidth enhancement ratio of 2.8.

TL;DR: This brief presents a nano-ampere CMOS current reference (CCR) for low power application with a wide temperature range from −40°C to 120°C with a simple division of a temperature-independent voltage and resistance in a simple way.