A roadmap for traffic engineering in SDN-OpenFlow networks

Software-Defined Networking

Software defined networks

Security of Software Defined Networks

This paper calls for rethinking packet-switch architectures by cutting all dependencies between the switch fabric and the linecards. Most single-stage packet-switch architectures rely on an instantaneous communication between the switch fabric and the linecards. Today, however, this assumption is breaking down, because effective propagation times are too high and keep increasing with the line rates. In this paper, we argue for a self-sufficient switch fabric by moving all the buffering from the linecards to the switch fabric. We introduce the crosspoint-queued (CQ) switch, a new buffered-crossbar switch architecture with large crosspoint buffers and no input queues, and show how it can be readily implemented in a single SRAM-based chip using current technology. For a crosspoint buffer size of one, we provide a closed-form throughput formula for all work-conserving schedules under uniform Bernoulli i.i.d. arrivals. Furthermore, we study the performance of the switch for larger buffer sizes and show that it nearly behaves as an ideal output-queued switch. Finally, we confirm our results using synthetic as well as trace-based simulations.

/pdf/the-crosspoint-queued-switch-2xgjgwj3tr.pdf

The Crosspoint-Queued Switch

OpenFlow is one of the most potential technique to enable innovation in network. To enable OpenFlow more flexibility and high-efficiency, multi-table pipeline has been introduced in OpenFlow. A HAL(Hardware Abstraction Layer) is proposed to address the incompatibility of flow table pipeline between legacy switch hardware and the controller. However, the burden of controller will be increased greatly. In this paper, an innovative middle layer called FlowAdapter is proposed. It converts flow entry rules from the controller flow table pipeline to switch hardware flow table pipeline, so that the same rules can be fitted into different types of hardware. With FlowAdapter, legacy OpenFlow hardware can be used to support multi-table pipeline rules. Located in switch, FlowAdapter is transparent to the controller. With a prototype implementation, we find that the FlowAdapter performs rules conversion effectively.

/pdf/the-flowadapter-enable-flexible-multi-table-processing-on-cscfaf4t9r.pdf

The FlowAdapter: enable flexible multi-table processing on legacy hardware

Scalability considerations drive the evolution of switch design from output queueing to input queueing and further to combined input and crosspoint queueing (CICQ). However, CICQ switches with credit-based flow control face new challenges of scalability and predictability. In this paper, we propose a novel approach of rate-based smoothed switching, and design a CICQ switch called the smoothed buffered crossbar or sBUX. First, the concept of smoothness is developed from two complementary perspectives of covering and spacing, which, commonly known as fairness and jitter, are unified in the same model. Second, a smoothed multiplexer sMUX is designed that allocates bandwidth among competing flows sharing a link and guarantees almost ideal smoothness for each flow. Third, the buffered crossbar sBUX is designed that uses the scheduler sMUX at each input and output, and a two-cell buffer at each crosspoint. It is proved that sBUX guarantees 100% throughput for real-time services and almost ideal smoothness for each flow. Fourth, an on-line bandwidth regulator is designed that periodically estimates bandwidth demand and generates admissible allocations, which enables sBUX to support best-effort services. Simulation shows almost 100% throughput and multi-microsecond average delay. In particular, neither credit-based flow control nor speedup is used, and arbitrary fabric-internal latency is allowed between line cards and the switch core, simplifying the switch implementation.

http://www.jdl.ac.cn/doc/2008/On%20guaranteed%20smooth%20switching%20for%20buffered%20crossbar%20switches.pdf

On guaranteed smooth switching for buffered crossbar switches

Ternary content addressable memories (TCAMs) are frequently used for fast matching of packets against a given ruleset. While TCAMs can achieve fast matching, they are plagued by high update costs that can make them unusable in a high churn rate environment. We present, in this paper, a systematic and in-depth analysis of the TCAM update problem. We apply partial order theory to derive fundamental constraints on any rule ordering on TCAMs, which ensures correct checking against a given ruleset. This theoretical insight enables us to fully explore the TCAM update algorithms design space, to derive the optimal TCAM update algorithm (though it might not be suitable to be used in practice), and to obtain upper and lower bounds on the performance of practical update algorithms. Having lower bounds, we checked if the smallest update costs are compatible with the churn rate observed in practice, and we observed that this is not always the case. We therefore developed a heuristic based on ruleset splitting, with more than a single TCAM chip, that achieves significant update cost reductions ( $1.05\sim 11.3\times $ ) compared with state-of-the-art techniques.

Partial Order Theory for Fast TCAM Updates

Programmable routers supporting virtualization are a key building block for bridging the gap between new Internet protocols and their deployment in real operational networks. This article presents the design and implementation of PEARL, a programmable virtual router platform with relatively high performance. It offers high flexibility by allowing users to control the configuration of both hardware and software data paths. The platform makes use of fast lookup in hardware and software exceptions in commodity multicore CPUs to achieve highspeed packet processing. Multiple isolated packet streams and virtualization techniques ensure isolation among virtual router instances.

/pdf/pearl-a-programmable-virtual-router-platform-20g9xv00qq.pdf

PEARL: a programmable virtual router platform

This invention relates to core router supportive visit and control sequence double shed compatible router finding device, which belongs to Internet core router hardware technique field. The invention is characterized by comprising package pre-process circuit element and parallel CAM and SRAM and forms one router and ACL list through TCAM system and supports the list items dynamic alignment. The package pre-process circuit elements receive the data package and process them and extract needed information and ACL filtered information and send to the TCAM system and decide package process means according to the requirement results.

Hongtao Guan

Papers

The FlowAdapter: enable flexible multi-table processing on legacy hardware

On guaranteed smooth switching for buffered crossbar switches

Partial Order Theory for Fast TCAM Updates

PEARL: a programmable virtual router platform

Double stack compatible router searching device supporting access control listing function on core routers