An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Vertical system integration

A dielectric film containing LaAlO 3 and method of fabricating a dielectric film contained LaAlO 3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO 2 . The LaAlO 3 gate dielectrics formed are thermodynamically stable such that these gate dielectrics will have minimal reactions with a silicon substrate or other structures during processing. A LaAlO 3 gate dielectric is formed by atomic layer deposition employing a lanthanum sequence and an aluminum sequence. A lanthanum sequence uses La(thd) 3 (thd=2,2,6,6-tetramethl-3,5-heptanedione) and ozone. An aluminum sequence uses either trimethylaluminium, Al(CH 3 ) 3 , or DMEAA, an adduct of alane (AlH 3 ) and dimethylehtylamine [N(CH 3 ) 2 (C 2 H 5 )], with distilled water vapor.

Atomic layer-deposited laaio3 films for gate dielectrics

A device includes a substrate, at least one dielectric layer positioned on said substrate, and metalization positioned in an opening in the at least one dielectric layer and extending a predetermined distance towards the substrate from a surface which is substantially coplanar with a surface of the at least one dielectric layer. The metalization includes a low resistivity metal or alloy encapsulated by a refractory metal or alloy having a resistivity greater than that of the low resistivity metal or alloy and having a columnar structure. The metalization has a plurality of sides in cross-section, at least three sides of the plurality of sides being substantially formed of a refractory metal or alloy having a common composition, at least two sides of the plurality of sides extending substantially the predetermined distance, and all of the plurality of sides being formed within the opening in the at least one dielectric layer.

Refractory metal capped low resistivity metal conductor lines and vias

An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Method of making an edge seal for a semiconductor device

A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity

A structure and method is disclosed for directly attaching a device or package on flexible organic circuit carriers having low cost and high reliability. IC chips with a new solder interconnect structure, comprised of a layer of pure tin, deposited on the top of high melting Pb--Sn solder balls are employed for joining. These methods, techniques and metallurgical structures enables direct attachment of electronic devices of any complexity to any substrate and to any level of packaging hierarchy. Also, devices or packages having other joining technologies, eg. SMT, BGA, TBGA, etc. could be joined onto the flexible circuit carrier.

Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder

A structure and method is disclosed for directly attaching a device or package on flexible organic circuit carriers having low cost and high reliability. IC chips with a new solder interconnect structure, comprised of a layer of pure tin, deposited on the top of high melting Pb—Sn solder balls are employed for joining. These methods, techniques and metallurgical structures enables direct attachment of electronic devices of any complexity to any substrate and to any level of packaging hierarchy. Also, devices or packages having other joining technologies, eg. SMT, BGA, TBGA, etc. could be joined onto the flexible circuit carrier.

Hormazdyar M. Dalal

Papers

Refractory metal capped low resistivity metal conductor lines and vias

Method of making an edge seal for a semiconductor device

Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity

Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder

Flip chip attach on flexible circuit carrier using chip with metallic cap on solder