L
Louis L. Hsu
Researcher at IBM
Publications - 411
Citations - 9829
Louis L. Hsu is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Field-effect transistor. The author has an hindex of 49, co-authored 411 publications receiving 9829 citations. Previous affiliations of Louis L. Hsu include GlobalFoundries.
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Patent
Refractory metal capped low resistivity metal conductor lines and vias
TL;DR: In this paper, the authors defined the notion of a columnar structure of a metalization, which is defined as a low resistivity metal or alloy encapsulated by a refractory metal having a resistivity greater than that of the low-resilience metal and having a common composition, and all the sides of the plurality of sides being formed within the opening in the at least one dielectric layer.
Patent
Intelligent wireless power charging system
TL;DR: In this paper, the authors proposed a system and methodology for intelligent power management of wirelessly networked devices, which provides reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device.
Patent
Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
TL;DR: In this article, a sub-micron FET is disclosed made by a method using expendable self-aligned gate structure up to and including the step of annealing the source/drain regions.
Patent
Vertical MOSFET SRAM cell
TL;DR: In this article, a method of forming an SRAM cell device includes the following steps: form pass gate FET transistors and form a pair of vertical pull-down FETtransistors with a first common body and a first source in a silicon layer patterned into parallel islands formed on a planar insulator.
Patent
Fuse processing using dielectric planarization pillars
TL;DR: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the substrate having a portion thereof containing electrical wiring and another, adjacent portion substantially free of electrical wiring; optionally, a further electrically and thermally resistive fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically INSulating layer as mentioned in this paper.