Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

/pdf/review-semiconductor-piezoresistance-for-microsystems-2i2jehwa4g.pdf

Review: Semiconductor Piezoresistance for Microsystems

With the increasing requirements for microelectromechanical systems (MEMS) regarding stability, miniaturization and integration, novel materials such as wide band gap semiconductors are attracting more attention. Polycrystalline SiC has first been implemented into Si micromachining techniques, mainly as etch stop and protective layers. However, the outstanding properties of wide band gap semiconductors offer many more possibilities for the implementation of new functionalities. Now, a variety of technologies for SiC and group III nitrides exist to fabricate fully wide band gap semiconductor based MEMS. In this paper we first review the basic technology (deposition and etching) for group III nitrides and SiC with a special focus on the fabrication of three-dimensional microstructures relevant for MEMS. The basic operation principle for MEMS with wide band gap semiconductors is described. Finally, the first applications of SiC based MEMS are demonstrated, and innovative MEMS and NEMS devices are reviewed.

http://iopscience.iop.org/article/10.1088/0022-3727/40/20/S19/pdf

Group III nitride and SiC based MEMS and NEMS: materials properties, technology and applications

Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.

Semiconductor processing system and methods using capacitively coupled plasma

An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

Semiconductor processing systems having multiple plasma configurations

The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control phys ...

/pdf/integrating-mems-and-ics-3tx6wanytd.pdf

Integrating MEMS and ICs

A method for the plasma-free etching of silicon using the etching gas ClF 3 or XeF 2 and its use are provided. The silicon is provided having one or more areas to be etched as a layer on the substrate or as the substrate material itself. The silicon is converted into the mixed semiconductor SiGe by introducing germanium and is etched by supplying the etching gas ClF 3 or XeF 2 . The introduction of germanium and the supply of the etching gas ClF 3 or XeF 2 may be performed at the same time or alternatingly. In particular, it is provided that the introduction of germanium be performed by implanting germanium ions in silicon.

Method for Accelerated Etching of Silicon

A method for packaging semiconductor chips and a corresponding semiconductor chip system. The method includes making available a semiconductor chip having a diaphragm region; providing a cap over the diaphragm region, while leaving the diaphragm region open; mounting the semiconductor chip on a support frame; and providing a molded housing around the semiconductor chip and at least a partial region of the support frame for packaging the semiconductor chip.

Method for mounting semiconductor chips and corresponding semiconductor chip system

Verfahren zur Herstellung eines Halbleiterbauelements (100; ...; 900; 1500; 1600), insbesondere eines Drucksensors, das ein Halbleitersubstrat (101) aus Silizium aufweist, wobei
 • in einem ersten Schritt eine erste porose Schicht (104) in dem Halbleiterbauelement (100; ...; 900; 1500; 1600) gebildet wird; und
 • in einem zweiten Schritt ein Hohlraum (201) aus einer zweiten porosen Schicht (105) unterhalb der ersten porosen Schicht (104;) in dem Halbleiterbauelement (100; ...; 900; 1500; 1600) gebildet wird; wobei
 • der zweite Schritt einen ersten Unterschritt aufweist, wahrend dem unter der ersten porosen Schicht (104) eine zweite porose Schicht (105) mit einer Porositat von mehr als ca. 70 % und weniger als 100 % gebildet wird; und
 • der Hohlraum (201) durch einen Temperschritt aus der zweiten porosen Schicht gebildet wird; und
 • die Poren auf der Oberflache der ersten porosen Schicht (104) durch den Temperschritt weitgehend verschlossen werden.

Verfahren zur herstellung eines halbleiterbauelements sowie ein nach dem verfahren hergestelltes halbleiterbauelement

We report a new surface micromachining technology to fabricate monocrystalline silicon membranes covering a vacuum cavity for applications like piezoresistive pressure sensors. The main process steps are: (i) local anodic etching of layered porous silicon with different porosities, (ii) thermal rearrangement of the porous silicon, and (iii) epitaxial growth of the silicon membrane layer. In contrast to conventional bulk micromachining the new technology has the benefit of a considerable freedom in the design of mono-crystalline silicon membranes. The membrane geometry is only determined by the porous region. Further, the new fabrication method is fully CMOS compatible. In fact, except for anodic etching, all process steps are part of a standard mixed signal IC production line. Various aspects of the used key process steps are discussed, particularly with regard to the oxygen and fluorine desorption during the porous silicon annealing. A piezoresistive pressure sensor with integrated ASIC based on the new fabrication method is demonstrated.

A novel micromachining process for the fabrication of monocrystalline Si-membranes using porous silicon

Es wird ein Verfahren zur Herstellung eines Halbleiterbauelements mit einem Halbleitertrager (1) vorgeschlagen, bei welchem fur die Ausbildung von frei tragenden Strukturen (3) fur ein Bauelement eine flachige porose Membranschicht (3) und eine Kavitat (2) unter der porosen Membranschicht (3) erzeugt wird. Die Erfindung hat die Aufgabe, eine Membranbeschadigung bei der Herstellung oder bei regelmasig auftretenden Anwendungsfallen zu vermeiden. Diese Aufgabe kann durch unterschiedliche Vorgehensweisen gelost werden. Bei einer ersten Losung erhalt der Halbleitertrager (1) im Membranbereich im Vergleich zur Kavitat eine unterschiedliche Dotierung, womit sich unterschiedliche Porengrosen und/oder Porositaten herstellen lassen, was bei der Kavitatserzeugung fur einen verbesserten Atzgastransport genutzt werden kann. Die Aufgabe kann jedoch auch dadurch gelost werden, dass im Membranbereich Mesoporen und im spateren Kavitatsbereich Nanoporen als Hilfsstruktur erzeugt werden. Im Weiteren wird unter anderem ein Halbleiterbauelement vorgeschlagen, das auf einem oder mehreren dieser Verfahren basiert.

Hubert Benzel

Papers

Method for Accelerated Etching of Silicon

Method for mounting semiconductor chips and corresponding semiconductor chip system

Verfahren zur herstellung eines halbleiterbauelements sowie ein nach dem verfahren hergestelltes halbleiterbauelement

A novel micromachining process for the fabrication of monocrystalline Si-membranes using porous silicon

Verfahren zur Herstellung eines Halbleiterbauelements sowie ein Halbleiterbauelement, insbesondere ein Membransensor