A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation For n-channel transistors the degradation is mainly caused by the generation of interface traps Only in the region of hole injection (V/sub g/ approximately=V/sub t/) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps The latter are nevertheless generated in comparable amounts as in n-channel transistors Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model >

Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs

The conditions of hot-carrier stressing of n-MOS transistors have been studied in order to investigate the types of damage arising from the stressing in the gate voltage range V/sub d//2>or=V/sub g/>or=V/sub d/. Although a maximum in the V/sub t/ degradation is seen at V/sub g/=V/sub d//2, considerable stress damage occurs at higher gate voltages (at and around V/sub g/=V/sub d/). This stress damage obeys a different power law as a function of time than that which is seen at V/sub g/=V/sub d//2. Examination of the damage using dynamic stress experiments and alternate static injection phases suggests that the oxide-trapped charge (N/sub ox/) is mostly responsible for the damage at V/sub g/=V/sub d/, whereas the degradation at V/sub g/=V/sub d//2 arises from the interface state (N/sub ss/) creation. An examination of the gate current conditions shows that the oxide traps are created under conditions of maximum electronic gate current, suggesting that the hot electrons are responsible for the damage. Analysis of the time evolution of the damage suggests that the two types of damage (N/sub ox/ and N/sub ss/) can be seen during a single stressing, depending on the stress voltage conditions. >

Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2>or=V/sub g/<or=V/sub d/) during hot-carrier stressing of n-MOS transistors

A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon in to an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.

Integrated circuit device having improved junction connections

An integrated circuit device, including a fingerprint sensing device, having an integrated circuit die, a body of encapsulating material surrounding the integrated circuit die and having an opening therein exposing a portion of the integrated circuit die, and an electrically conductive member or frame being mounted to the body of encapsulating material adjacent the opening. The electrically conductive member is adhesively secured to the integrated circuit die. Accordingly, the adhesive and electrically conductive member may serve as a seal to the interface between the body of encapsulating material and the die. It also may define a frame that surrounds a body of removable material during an intermediate stage in manufacturing. The body of removable material and its frame may be positioned on the integrated circuit die while plastic is injection molded to encapsulate the assembly.

Integrated circuit device having an opening exposing the integrated circuit die and related methods

When the p-channel MOSFET is stressed near the maximum substrate current I sub , the lifetime t (5-percent increase in the transconductance) follows tI_{sub} = A(I_{sub}/I_{d})^{-n} , with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratio I_{sub}/I_{d} and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.

Hot-carrier-induced degradation in p-channel LDD MOSFET's

The n-channel LDD MOSFET lifetime is observed to follow \tau=(A/I_{d})(I_{sub}/I_{d})^{-n} from 77 to 295 K when the device is stressed near the maximum I sub . Here I d is the drain current and A is the proportionality constant. The experimental result indicates that n is approximately 2.7 and is independent of temperature. However, the proportionality constant A follows A = A_{0} \exp (-E_{a}/kT) , with E_{a} = 39 meV. The smaller proportionality constant at low temperatures suggests that hot-electron injection (HEI) degradation is caused by the electron trapping in the oxide.

Hot-electron-induced MOSFET degradation at low temperatures

An improved process for fabricating a static RAM cell having a polysilicon load resistance is provided. Following formation of source, gate and drain regions, a planarized dielectric structure is formed over the junction regions, and via openings which expose portions of the source and drain regions are created. The via openings are filled with polysilicon interconnects, appropriately doped for low resistance contacts. Where the contact includes a resistor load, the polysilicon is not doped. Thus, the prior art approach of providing doped and undoped regions along the same polysilicon interconnect is not employed. Rather, the doped and undoped regions are physically separated. Consequently, the minimum length of the poly load is limited only by the ability to form via openings of small dimensions.

Plugged poly silicon resistor load for static random access memory cells

Experimental results are presented to show that, for temperatures ranging from 27°C to 110°C, the generation of the positive charges during a constant current stress decreases with increasing temperature whereas the generation of the interface states increases with increasing temperature. Since the oxide breakdown and the interface state have the same temperature dependence, it appears that the oxide breakdown is related to the generation of the interface states.

Temperature dependence of charge generation and breakdown in SiO 2

A fabrication method and resulting integrated circuit structure that provide a second level of interconnect, a low resistance contact strap between underlying layers which is not sensitive to alignment and low lateral diffusion polysilicon load. The method comprises the steps of providing contact openings in an insulating layer on a wafer to any desired underlying circuit layers, depositing a silicide layer on the wafer, removing selected portions of the silicide layer, depositing a polysilicon layer on the wafer, lightly doping the polysilicon layer to a level appropriate for the resistor, and then removing portions of the polysilicon along with underlying silicide.

Hugo W. K. Chan

Papers

Hot-carrier-induced degradation in p-channel LDD MOSFET's

Hot-electron-induced MOSFET degradation at low temperatures

Plugged poly silicon resistor load for static random access memory cells

Temperature dependence of charge generation and breakdown in SiO 2

Method of forming a low resistance quasi-buried contact