Described herein are apparatus comprising one or more silicon-containing layers and a metal oxide layer. Also described herein are methods for forming one or more silicon-containing layers to be used, for example, as passivation layers in a display device. In one particular aspect, the apparatus comprises a transparent metal oxide layer, a silicon oxide layer and a silicon nitride layer. In this or other aspects, the apparatus is deposited at a temperature of 350° C. or below. The silicon-containing layers described herein comprise one or more of the following properties: a density of about 1.9 g/cm3 or greater; a hydrogen content of about 4×1022 cm−3 or less, and a transparency of about 90% or greater at 400-700 nm as measured by a UV-visible light spectrometer.

Barrier materials for display devices

Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length

Vertical nanowire transistor with axially engineered semiconductor and gate metallization

A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

Nonplanar iii-n transistors with compositionally graded semiconductor channels

A vertical tunneling field effect transistor (TFET) and method for forming a vertical TFET is disclosed. The vertical TFET comprises a vertical core region, a vertical source region, a vertical drain region and a gate structure. The vertical core region extends perpendicularly from a semiconductor substrate, has a top surface, consists of a doped outer part and a middle part. The vertical source region of semiconducting core material comprises the doped outer part of the vertical core region. The vertical drain region of semiconducting drain material comprises along its longitudinal direction a first drain part and a second drain part, the first drain part either directly surrounding said vertical source region or directly sandwiching said vertical source region between two sub-parts of said first drain part, the second drain part located directly above and in contact with the first drain part. The gate structure comprises a gate dielectric layer directly aside of the first drain part of the vertical drain region and a gate layer directly aside of the gate dielectric layer. The second drain part extends above the gate layer and gate dielectric layer. The vertical TFET further comprises a drain contact directly connected to a third drain part, the third drain part being an upper part of the second drain part of the vertical drain region. The vertical TFET further comprises a source contact electrically connected to the vertical source region. The vertical TFET further comprises a gate contact electrically connected to the gate layer.

Tunnel field effect transistor and method for making thereof

According to example embodiments, a graphene switching devices having a tunable barrier includes a semiconductor substrate that includes a first well doped with an impurity, a first electrode on a first area of the semiconductor substrate, an insulation layer on a second area of the semiconductor substrate, a graphene layer on the insulation layer and extending onto the semiconductor substrate toward the first electrode, a second electrode on the graphene layer and insulation layer, a gate insulation layer on the graphene layer, and a gate electrode on the gate insulation layer. The first area and the second area of the semiconductor substrate may be spaced apart from each other. The graphene layer is spaced apart from the first electrode. A lower portion of the graphene layer may contact the first well. The first well is configured to form an energy barrier between the graphene layer and the first electrode.

Graphene switching device having tunable barrier

A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.

Huili (Grace) Xing

Papers

Low voltage tunnel field-effect transistor (tfet) and method of making same