To improve color reproduction areas in a display device having light-emitting elements. A display region has a plurality of picture elements. Each picture element includes: first and second pixels each including a light-emitting element which has a chromaticity whose x-coordinate in a CIE-XY chromaticity diagram is 0.50 or more; third and fourth pixels each including a light-emitting element which has a chromaticity whose y-coordinate in the diagram is 0.55 or more; and fifth and sixth pixels each including a light-emitting element which has a chromaticity whose x-coordinate and y-coordinate in the diagram are 0.20 or less and 0.25 or less, respectively. The light-emitting elements in the first and second pixels have different emission spectrums from each other; the light-emitting elements in the third and fourth pixels have different emission spectrums from each other; and the light-emitting elements in the fifth and sixth pixels have different emission spectrums from each other.

Display device and electronic device

A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

Integrated circuit device and method of manufacturing the same

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

Gate contact structure over active gate and method to fabricate same

FinFET devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a FET device includes the following steps. A wafer is provided having an active layer on an insulator. A plurality of fin hardmasks are patterned on the active layer. A dummy gate is placed over a central portion of the fin hardmasks. One or more doping agents are implanted into source and drain regions of the device. A dielectric filler layer is deposited around the dummy gate. The dummy gate is removed to form a trench in the dielectric filler layer. The fin hardmasks are used to etch a plurality of fins in the active layer within the trench. The doping agents are activated. A replacement gate is formed in the trench, wherein the step of activating the doping agents is performed before the step of forming the replacement gate.

Fin-Last Replacement Metal Gate FinFET

An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric.

Extremely Thin Semiconductor-On-Insulator (ETSOI) FET With A Back Gate and Reduced Parasitic Capacitance And Method of Forming The Same

The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners.

Huilong Zhu

Papers

Semiconductor structure and method for manufacturing the same