Patent
Semiconductor structure and method for manufacturing the same
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TLDR
In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.Abstract:
The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners.read more
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References
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Chemical Mechanical Planarization of Microelectronic Materials
TL;DR: In this article, historical perspective CMP: variables and manipulations electrochemical and mechanical concepts for CMP processes copper CMP CMP of other materials post CMP cleaning, and a discussion of the relationship between CMP and manipulation.
Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
Patent
High density data storage using stacked wafers
TL;DR: In this paper, a solid-state memory unit is constructed using stacked wafers containing a large number of memory units in each wafer, and vertical connections between them are created using bumps at the contact points and metal in through-holes aligned with the bumps.
Patent
Semiconductor device and method of fabricating the same
TL;DR: In this article, a tensile tensile stress is formed on the substrate to relax a compressive stress existing in the channel region, and the second nitride layer having actual compressive stresses is formed to cover the p-channel MOSFET.
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Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication
Anthony J. Lochtefeld,Matthew T. Currie,Zhiyuan Cheng,James Fiorenza,G. Braithwaite,T. A. Langdo +5 more
TL;DR: In this paper, the fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations is discussed.