An information terminal apparatus capable of ensuring enhanced operational facility and realizing easier maintenance of software required for a variety of services. The terminal apparatus includes an external information input port for receiving external software transmitted thereto by radio waves; a first memory for storing the software received by the external information input port; a first controller operated in accordance with the execution of the software stored in the first memory; a console for inputting predetermined data in conformity with the execution of the software; and a display for visually representing various kinds of information in conformity with the execution of the software. The software is obtained via a cable box for transferring a signal to or from the information terminal unit. The cable box includes an interface for transferring information to and from a host processor; a second memory for storing the software transmitted thereto from the host processor; and a second controller for controlling the signal transfer to or from the interface, the second memory and the information terminal unit.

Information terminal apparatus that is remotely programmed by radio waves and that displays input keys of program functions on a display

A universal remote control unit for controlling the operation of a plurality of devices such as a cable box, a television, a video device, and an audio device, includes a processor having a plurality of operating modes. In one embodiment the universal remote control unit includes an ALL key preprogrammed to allow a user to turn on or off all of the devices. In another embodiment, a remote control unit allows assigning an additional function to a key having a preprogrammed function.

Universal remote control unit

Foamed cellular polymer particles having various physical properties made by use of foaming of the polymer containing a blowing agent. The foamed particles can be shipped in packages having less strenght than the packages used to ship the expandable particles and is more covenient for the user because there is no need for the party who receives them to have equipment to impregnate them with blowing agent and foam them.

Foamed cellular particles of an expandable polymer composition

Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures, after decades of research efforts. Near-bank PIM architectures place simple cores close to DRAM banks. Recent research demonstrates that they can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwidth and low memory access latency, thereby being a good fit to accelerate the Sparse Matrix Vector Multiplication (SpMV) kernel. SpMV has been characterized as one of the most significant and thoroughly studied scientific computation kernels. It is primarily a memory-bound kernel with intensive memory accesses due its algorithmic nature, the compressed matrix format used, and the sparsity patterns of the input matrices given. This paper provides the first comprehensive analysis of SpMV on a real-world PIM architecture, and presents SparseP, the first SpMV library for real PIM architectures. We make two key contributions. First, we design efficient SpMV algorithms to accelerate the SpMV kernel in current and future PIM systems, while covering a wide variety of sparse matrices with diverse sparsity patterns. Second, we provide the first comprehensive analysis of SpMV on a real PIM architecture. Specifically, we conduct our rigorous experimental analysis of SpMV kernels in the UPMEM PIM system, the first publicly-available real-world PIM architecture. Our extensive evaluation provides new insights and recommendations for software designers and hardware architects to efficiently accelerate the SpMV kernel on real PIM systems. For more information about our thorough characterization on the SpMV PIM execution, results, insights and the open-source SparseP software package [21], we refer the reader to the full version of the paper [3, 4]. The SparseP software package is publicly and freely available at https://github.com/CMU-SAFARI/SparseP.

Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures

Many modern workloads, such as neural networks, databases, and graph processing, are fundamentally memory-bound. For such workloads, the data movement between main memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bound workloads is insufficient to amortize the cost of main memory access. Fundamentally addressing this data movement bottleneck requires a paradigm where the memory system assumes an active role in computing by integrating processing capabilities. This paradigm is known as processing-in-memory (PIM). Recent research explores different forms of PIM architectures, motivated by the emergence of new 3D-stacked memory technologies that integrate memory with a logic layer where processing elements can be easily placed. Past works evaluate these architectures in simulation or, at best, with simplified hardware prototypes. In contrast, the UPMEM company has designed and manufactured the first publicly-available real-world PIM architecture. The UPMEM PIM architecture combines traditional DRAM memory arrays with general-purpose in-order cores, called DRAM Processing Units (DPUs), integrated in the same chip. This paper provides the first comprehensive analysis of the first publicly-available real-world PIM architecture. We make two key contributions. First, we conduct an experimental characterization of the UPMEM-based PIM system using microbenchmarks to assess various architecture limits such as compute throughput and memory bandwidth, yielding new insights. Second, we present PrIM (Processing-In-Memory benchmarks), a benchmark suite of 16 workloads from different application domains (e.g., dense/sparse linear algebra, databases, data analytics, graph processing, neural networks, bioinformatics, image processing), which we identify as memory-bound. We evaluate the performance and scaling characteristics of PrIM benchmarks on the UPMEM PIM architecture, and compare their performance and energy consumption to their modern CPU and GPU counterparts. Our extensive evaluation conducted on two real UPMEM-based PIM systems with 640 and 2,556 DPUs provides new insights about suitability of different workloads to the PIM system, programming recommendations for software designers, and suggestions and hints for hardware and architecture designers of future PIM systems.

https://ieeexplore.ieee.org/ielx7/6287639/6514899/09771457.pdf

Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System

Emerging applications such as deep neural network demand high off-chip memory bandwidth. However, under stringent physical constraints of chip packages and system boards, it becomes very expensive to further increase the bandwidth of off-chip memory. Besides, transferring data across the memory hierarchy constitutes a large fraction of total energy consumption of systems, and the fraction has steadily increased with the stagnant technology scaling and poor data reuse characteristics of such emerging applications. To cost-effectively increase the bandwidth and energy efficiency, researchers began to reconsider the past processing-in-memory (PIM) architectures and advance them further, especially exploiting recent integration technologies such as 2.5D/3D stacking. Albeit the recent advances, no major memory manufacturer has developed even a proof-of-concept silicon yet, not to mention a product. This is because the past PIM architectures often require changes in host processors and/or application code which memory manufacturers cannot easily govern. In this paper, elegantly tackling the aforementioned challenges, we propose an innovative yet practical PIM architecture. To demonstrate its practicality and effectiveness at the system level, we implement it with a 20nm DRAM technology, integrate it with an unmodified commercial processor, develop the necessary software stack, and run existing applications without changing their source code. Our evaluation at the system level shows that our PIM improves the performance of memory-bound neural network kernels and applications by 11.2× and 3.5×, respectively. Atop the performance improvement, PIM also reduces the energy per bit transfer by 3.5×, and the overall energy efficiency of the system running the applications by 3.2×.

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product

A mode conversion method for performing an input/output of the control data in a multifunctional programmable remote controller having multi-band remote function and learning functions, including the steps of checking for which key is selected among a mode key, a set key, and normal keys, converting to a waiting mode when the setting is not in progress if a key signal is not input, and displaying the selected mode within a certain time and converting to a using mode when the setting is in progress, then, inspecting the setting condition if the mode key is selected so that if the setting is not in progress, each mode display is toggled to indicate that the mode is converted, and if the setting is in progress, the current step returns to a key scanning step for determining whether the current mode is a using mode or a setting mode so that if it is the using mode, data is output and displayed by modes and if it is the setting mode, the mode is selected.

Mode conversion method for multifunctional programmable remote controller

A key scan circuit and the method thereof in a microcomputer is disclosed which requires no diode for preventing circuit short and performs key check or automatic operations with a simplified circuit structure. The key scan method includes a step of designating the input/output mode of a bilateral port by a data direction register in a microcomputer which includes an input/output bilateral port and an input only unilateral port, so as to prevent circuit shorts when more than one key are pushed. Further, by using first and second memories, the key scan method includes a step of determining whether the number of logic low states in the first memory is greater than one, and determining whether the number of logic high states stored in the second memory is greater than one, thus indicating the pressing of multiple keys. Then, the pushed key's value is determined by a predetermined formula by obtaining the value m when the mth bit value of the first memory is logic low, and the value n when the nth bit value of the second memory is logic high.

Hyeon-Su Kim

Papers

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product

Mode conversion method for multifunctional programmable remote controller

Key scan circuit and method in a microcomputer system

Verfahren und schaltkreis zum abtasten von tasten fuer ein mikrocomputersystem

Betriebsartumwandlungsverfahren fuer eine multifunktionale programmierbare fernbedienung