K
Kyomin Sohn
Researcher at Samsung
Publications - 69
Citations - 727
Kyomin Sohn is an academic researcher from Samsung. The author has contributed to research in topics: Semiconductor memory & Signal. The author has an hindex of 12, co-authored 61 publications receiving 488 citations. Previous affiliations of Kyomin Sohn include KAIST.
Papers
More filters
Journal ArticleDOI
A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture
Sungdae Choi,Kyomin Sohn,Min-Wuk Lee,Sunyoung Kim,Hye-Mi Choi,Dong-Hyun Kim,Uk-Rae Cho,Hyun-Geun Byun,Yun-Seung Shin,Hoi-Jun Yoo +9 more
TL;DR: A hidden bank selection scheme is proposed to activate limited amount of cells during the search operation avoiding additional timing penalty, and match fine repeaters and sub-match fine scheme are used for fast NAND search operation.
Proceedings ArticleDOI
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product
Sukhan Lee,Shin-haeng Kang,Jae-Hoon Lee,Hyeon-Su Kim,Eojin Lee,Seung-Woo Seo,Hosang Yoon,Seung-Won Lee,Kyoung-Hwan Lim,Hyun-Sung Shin,Jin-Hyun Kim,O Seongil,Anand Iyer,Wang David T,Kyomin Sohn,Nam Sung Kim +15 more
TL;DR: Wang et al. as discussed by the authors proposed an innovative yet practical processing-in-memory (PIM) architecture, which improves the performance of memory-bound neural network kernels and applications by 11.2× and 3.5× respectively.
Proceedings ArticleDOI
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications
Young-Cheon Kwon,Sukhan Lee,Jae-Hoon Lee,Sang-Hyuk Kwon,Je Min Ryu,Jong-Pil Son,O Seongil,Hak-soo Yu,Hae-Suk Lee,Soo-Young Kim,Young-min Cho,Jin Guk Kim,Jongyoon Choi,Hyun-Sung Shin,Jin Kim,Bengseng Phuah,Hyoung-Min Kim,Myeong Jun Song,Ahn Choi,Daeho Kim,SooYoung Kim,Eun-Bong Kim,Wang David T,Shin-haeng Kang,Yu-Hwan Ro,Seung-Woo Seo,Joon-Ho Song,Jae-Youn Youn,Kyomin Sohn,Nam Sung Kim +29 more
TL;DR: FIMDRAM as discussed by the authors integrates a 16-wide single-instruction multiple-data engine within the memory banks and exploits bank-level parallelism to provide $4 \times higher processing bandwidth than an off-chip memory solution.
Journal ArticleDOI
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme
Kyomin Sohn,Taesik Na,In-Dal Song,Yong Shim,Won-Il Bae,Sang-Hee Kang,Dong Su Lee,Han-Gyun Jung,Hanki Jeoung,Ki-Won Lee,Junsuk Park,Jongeun Lee,Byung-Hyun Lee,Inwoo Jun,Ju-Seop Park,Junghwan Park,Hundai Choi,Sang Hee Kim,Haeyoung Chung,Young Sang Choi,Dae-Hee Jung,Jang Seok Choi,Byung-sick Moon,Jung-Hwan Choi,Byung-Chul Kim,Seong-Jin Jang,Joo Sun Choi,Kyung Seok Oh +27 more
TL;DR: Dual error detection scheme is proposed to guarantee the reliability of signals, and gain enhanced buffer and PVT tolerant data fetch scheme are adopted for CA and DQ respectively to reduce the output jitter.
Journal ArticleDOI
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution
Kyomin Sohn,Won-Joo Yun,Reum Oh,Chi-Sung Oh,Seong-young Seo,Min-Sang Park,Dong-Hak Shin,Won-Chang Jung,Sang-hoon Shin,Je-Min Ryu,Hye-Seung Yu,Jae-Hun Jung,Hyunui Lee,Seok-Yong Kang,Young-Soo Sohn,Jung-Hwan Choi,Yong-Cheol Bae,Seong-Jin Jang,Gyo-Young Jin +18 more
TL;DR: The 2nd generation HBM is proposed to double the bandwidth to more than 256GB/s and support pseudo-channel mode and 8H stacks, and an adaptive refresh considering temperature distribution (ART) scheme as a solution.