O Seongil

TL;DR: Wang et al. as discussed by the authors proposed an innovative yet practical processing-in-memory (PIM) architecture, which improves the performance of memory-bound neural network kernels and applications by 11.2× and 3.5× respectively.

TL;DR: FIMDRAM as discussed by the authors integrates a 16-wide single-instruction multiple-data engine within the memory banks and exploits bank-level parallelism to provide $4 \times higher processing bandwidth than an off-chip memory solution.

TL;DR: This work identifies that aggressive miniaturization makes DRAM cells more sensitive to random telegraph noise or variable retention time, which is dominantly manifested as a surge in randomly scattered single-cell faults, and advocates using In-DRAM ECC to overcome the DRAM scaling challenges and architecture to accomplish high area efficiency and minimal performance degradation.

TL;DR: A high-density managed DRAM architecture, dubbed 3D-XPath for applications demanding both low latency and high capacity for memory, that allows unused memory channels to service memory requests from applications when primary channels supposed to handle the memory requests are blocked by page transfers at given moments, considerably increasing the high-percentile response time.

TL;DR: This paper has successfully implemented a 9.5Gb/s/pin 16Gb LPDDR5X using a fourth generation 10nm DRAM fabrication technology and has new high-speed enabling features: per-pin DFE training, pre-emphasis for DQ driver, receiver offset calibration training, and a read duty-cycle adjuster.