Hyunsun Park

TL;DR: In order to reduce DRAM refresh energy which occupies a significant portion of total memory energy, a runtime-adaptive method of DRAM decay is presented and two methods, DRAM bypass and dirty data keeping, are presented for further reduction in refresh energy and memory access latency.

TL;DR: A probabilistically managed table (called PRoHIT) implemented on the DRAM chip that keeps track of victim row candidates in a probabilistic way and, in case of auto-refresh, the topmost entry is additionally refreshed thereby mitigating the row hammering problem.

TL;DR: This work proposes a low-overhead and efficient hardware mechanism that skips multiplications that will always give zero results regardless of input data, and presents data reuse optimization for addition operations in Winograd convolution (called AddOpt), which improves the utilization of local registers, thereby reducing on-chip cache accesses.

TL;DR: In this paper, an energy-efficient inner-product engine that utilizes the input feature map sparsity was proposed to implement an efficient neural processing unit (NPU) architecture for a Samsung flagship mobile system-on-chip.

TL;DR: This work developed a scalable, practical DIMM-based NMP solution tailor-designed for accelerating the inference serving of personalized recommendation system using industry-representative recommendation framework and experimentally validated the performance of a two-ranked AxDIMM prototype.