Silicon-based heterostructures have come a long way from the discovery of strain as a new and essential parameter for band structure engineering to the present state of electron and hole mobilities, which surpass those achieved in the traditional material combination by more than an order of magnitude and are rapidly approaching the best III - V heteromaterials. It is the purpose of this article to report on the most recent developments, and the performance level achieved to date in this material system, in a concise and critical manner. The first part of this review is concerned with the structural and electronic properties of the lattice-mismatched Si/SiGe heterostructure. Emphases are put on the effects of strain both on the band structure and on the band offsets, as well as on means to actually control the strain in a stack of heteroepitaxial layers. The second part is dedicated to the transport properties of low-dimensional carrier systems in Si/SiGe and Ge/SiGe heterostructures. The prospects and limitations of the different layer concepts are discussed in terms of scattering mechanisms and experimental results. This part also reviews the most recent magneto-transport experiments on quantum wires and quantum point contacts, which became possible by the enhanced mean free paths in these materials. The third part covers the device aspects of these high-mobility materials, which is of special interest, because silicon-based heterostructures can significantly enhance the performance level of contemporary Si devices without sacrificing the essential compatibility with standard Si technologies. The recent achievements in this application-driven research field, but also the foreseeable problems and limitations, are discussed, and an assessment of the possible role of such heterodevices in future microelectronic circuits is given.

http://iopscience.iop.org/article/10.1088/0268-1242/12/12/001/pdf

High-mobility Si and Ge structures

The high room-temperature carrier mobilities which have recently been observed for both electrons and holes in Si/SiGe heterostructures and the possibility of further improvements offer the prospect of silicon-based field effect transistors (FETs) with performances matching those of bipolar transistors and III-V modulation-doped FETs. In this article the electrical properties of this semiconductor system and the associated materials challenges are discussed, and some of the more important device applications are reviewed.

http://iopscience.iop.org/article/10.1088/0022-3727/31/12/003/pdf

SiGe heterostructures for FET applications

Si/SiGe/Si pMOS performance : alloy scattering and other considerations

In this study, admittance spectroscopy is applied for the first time to MOS capacitors fabricated on Si/Si/sub 1-x/Ge/sub x//Si double-heterostructures, in order to evaluate the valence band discontinuity /spl Delta/E/sub v/ at the Si/Si/sub 1-x/Ge/sub x/ interface. The principle of the measurement is presented and verified by the experimental results. A new feature of admittance spectroscopy applied to MOS capacitors is the ability to select the interface whose barrier is measured, by controlling the gate voltage. This fact is confirmed by the measurement of MOS capacitors, which include a SiGe well with different Ge contents at the front and the back interfaces. It is found from this measurement that, while /spl Delta/E/sub v/ at the back interface of the double-heterostructure is measured under slight depletion conditions for MOS capacitors, /spl Delta/E/sub v/ averaged between the front and the back interfaces is measured under accumulation conditions. The Ge/sub x/ content dependence of the measured /spl Delta/E/sub v/ is found to be in fairly good agreement with the theoretical values.

Evaluation of the valence band discontinuity of Si/Si/sub 1-x/Ge/sub x//Si heterostructures by application of admittance spectroscopy to MOS capacitors

This paper critically reviews the different mechanisms impacting the current-voltage and capacitance voltage characteristics of complementary metal oxide semiconductor (CMOS) compatible p-n junctions. Special attention is given to the influence of high doping density/high electric fields, mechanical stress and the presence of a hetero-junction either at the junction or in the depletion region. The basic mechanisms reported in the literature are checked for their validity for state-of-the-art structures and processing techniques. Critical issues are pointed out and illustrated for advanced CMOS compatible hetero-junctions, where high-field effects, like trap-assisted tunneling (TAT) and band-to-band-tunneling (BTBT) play a prominent role. The presence of an isotype hetero-junction gives rise to frequency dispersion in the depletion layer capacitance, which becomes more pronounced in combination with grown-in or processing-induced defects at the hetero-interface. Finally, the challenges and opportunities for future devices are addressed.

High Doping Density/High Electric Field, Stress and Heterojunction Effects on the Characteristics of CMOS Compatible p-n Junctions

The valence band offsets in Si/Si1-yGey/Si strained-layer heterostructures with 0<y<0.14 have been determined by CV measurements and from the analysis of Kroemer. Good agreement is obtained with theoretical predictions of values in the range 0 to 0.1 eV. Extracted interface charge densities are consistent with values deduced from parallel transport measurements in 2DHG structures.

I. D. Hawkins

Papers

The determination of valence band discontinuities and interface charge densities in Si/Si1-yGey/Si heterojunctions