FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<<ETX>>

Extraction and Simulation of Realistic CMOS Faults using

In order to reduce production costs of RF devices, it is important to remove bad circuits very early in the production flow. It is all the more true for dies designed to be integrated in complex systems. Thus highly efficient RF wafer testing is mandatory for those applications to prevent the loss of assembled systems due to defective RF dies. The problem is that current RF probing technologies hardly fulfill the industrial test requirements in terms of accuracy, reliability and cost. The proposed method proves to be a very interesting alternative to validate RF parameters with no need of expensive RF equipments (RF probes and RF automated test equipments (ATE)). A new test strategy based on DC or very low frequency (LF) measurements, which allows the elimination of expensive RF tests, is presented. The main idea is to insert some simple design for test (DfT) circuitry within the chip. This DfT provides relevant information on the structural behavior of the device blocks. The internal node data are additional to standard DC test measurements like power supply current or advanced DC test signatures (e.g. Vdd ramping), and LF measurements like gain in loopback mode. Since RF performance of each block is directly related to such structural data, it is possible to predict the RF characteristics of the blocks without time consuming RF measurements. RF parameters estimation is performed using nonlinear Artificial Neural Networks.

Combining Internal Probing with Artificial Neural Networks for Optimal RFIC Testing

The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques such as neural networks have been employed to automate classification. The major drawback to such techniques has been the implicit assumption that the variances of the responses of faulty circuits have been the same as each other and the same as that of the fault-free circuit. This assumption can be shown to be false. Neural networks, moreover, have proved to be slow. This paper describes a new neural network structure that clusters responses assuming different means and variances. Sophisticated statistical techniques are employed to handle situations where the variance tends to zero, such as happens with a fault that causes a response to be stuck at a supply rail. Two example circuits are used to show that this technique is significantly more accurate than other classification methods. A set of responses can be classified in the order of 1 s.

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Applying a robust heteroscedastic probabilistic neural network to analog fault detection and classification

Dynamic supply current (IDD) analysis has emerged as an effective way for defect oriented testing of analog circuits. In this paper, we propose using wavelet decomposition of IDD for fault detection in analog circuits. Wavelet transform has the property of resolving events in both time and frequency domain simultaneously unlike Fourier expansion which localizes a signal in terms of frequency only. Wavelet transform also has better sub-banding property and it can be easily adapted to current waveforms from different circuits. These make wavelet a more suitable candidate for fault detection in analog circuits than pure time-domain or pure frequency-domain methods. We have shown that for equivalent number of spectral components, sensitivity of wavelet based fault detection is much higher than Fourier or time-domain analysis for both catastrophic and parametric faults. Simulation results on benchmark circuits show that wavelet based method is on average 25 times more sensitive than DFT (Discrete Fourier Transform) for parametric faults and can be considered as a promising alternative for analog fault detection amidst measurement hardware noise and process variation.

Dynamic supply current testing of analog circuits using wavelet transform

This paper introduces a computer-aided-test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence design framework environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past approaches. In this paper, the use of this platform is illustrated for test optimization for the case of a fully differential amplifier. Test limits are set using a statistical circuit performance analysis that accounts for process deviations. Test metrics are estimated using this analysis. Specification-based tests are next optimized in terms of their capability of detecting catastrophic faults

CAT platform for analogue and mixed-signal test evaluation and optimization

The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analogue multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold, although they appear lower.

I.M. Bell

Papers

Generation and verification of tests for analogue circuits subject to process parameter deviations