Gallium-nitride power transistor (GaN HEMT) and integrated circuit technologies have matured dramatically over the last few years, and many hundreds of thousands of devices have been manufactured and fielded in applications ranging from pulsed radars and counter-IED jammers to CATV modules and fourth-generation infrastructure base-stations. GaN HEMT devices, exhibiting high power densities coupled with high breakdown voltages, have opened up the possibilities for highly efficient power amplifiers (PAs) exploiting the principles of waveform engineered designs. This paper summarizes the unique advantages of GaN HEMTs compared to other power transistor technologies, with examples of where such features have been exploited. Since RF power densities of GaN HEMTs are many times higher than other technologies, much attention has also been given to thermal management-examples of both commercial “off-the-shelf” packaging as well as custom heat-sinks are described. The very desirable feature of having accurate large-signal models for both discrete transistors and monolithic microwave integrated circuit foundry are emphasized with a number of circuit design examples. GaN HEMT technology has been a major enabler for both very broadband high-PAs and very high-efficiency designs. This paper describes examples of broadband amplifiers, as well as several of the main areas of high-efficiency amplifier design-notably Class-D, Class-E, Class-F, and Class-J approaches, Doherty PAs, envelope-tracking techniques, and Chireix outphasing.

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A Review of GaN on SiC High Electron-Mobility Power Transistors and MMICs

A large-signal model for HEMTs and MESFETs, capable of modeling the current-voltage characteristic and its derivatives, including the characteristic transconductance peak, gate-source and gate-drain capacitances, is proposed. Model parameter extraction is straightforward and is demonstrated for different submicron gate-length HEMT devices including different delta -doped pseudomorphic HEMTs on GaAs and lattice matched to InP, and a commercially available MESFET. Measured and modeled DC and S-parameters are compared and found to coincide well. >

A new empirical nonlinear model for HEMT and MESFET devices

R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned. >

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

A simple, general, yet realistic MOSFET model, the nth power law MOSFET model, is introduced. The model can express I-V characteristics of short-channel MOSFETs at least down to 0.25- mu m channel length and of resistance inserted MOSFETs. The model evaluation time is about 1/3 of the evaluation time of the SPICE3 MOS LEVEL3 model. The model parameter extraction is done by solving single variable equations and thus can be done within a second, unlike the fitting procedure with expensive numerical iterations used for the conventional models. The model also permits analytical treatment of circuits in the short-channel region and plays the role of a bridge between complicated MOSFET current characteristics and circuit behavior in the deep-submicrometer region. >

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A simple MOSFET model for circuit analysis

This paper describes a new, general and accurate, large signal GaAs FET model for nonlinear (e.g. harmonic balance) circuit simulation, its fast and unambiguous construction (model generation) by explicit calculations applied to the raw device data, and the adaptive, automated data acquisition system used to characterize the device. The model implementation in a harmonic balance simulator, the model generation procedure, and the automated data acquisition system form an efficient, practical, commercially available package. for state-of-the-art nonlinear circuit design.

Technology Independent Large Signal Non Quasi-Static FET Models by Direct Construction from Automatically Characterized Device Data

We have developed a GaAs FET model suitable for SPICE Circuit simulations. The dc equations are accurate to about 1 percent of the maximum drain current. A simple but accurate interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square-root law for larger values of the drain current. The ac equations, with charge-storage elements, describe the variation of the gate-to-source and gate-to-drain capacitances as the drain-to-source voltage approaches zero and when this voltage becomes negative. Under normal operating conditions the gate-to-source capacitance is much larger than the gate-to-drain capacitance. At zero drain-to-source voltage both capacitances are about equal. For negative drain-to-source voltages the original source acts like a drain and vice versa. Consequently the normally large gate-to-source capacitance becomes small and acts like a gate-to-drain capacitance. In order to model these effect it is necessary to realize that, contrary to conventional SPICE usage, there are no separate gate-to-source and gate-to-drain charges, but that there is only one gate Charge which is a function of gate-to-source and gate-to-drain voltages. The present treatment Of these capacitances permits simulations-in which the drain-to-source voltage reverses polarity, as occurs in pass-gate circuits.

GaAs FET device and circuit simulation in SPICE

It is shown that source and drain charges are not state variables in an FET, especially for source-drain voltages near zero. This behavior, observed in the model proposed in [2], is a genuine manifestation of the physics of FET's and is not a sign of improper behavior in a circuit simulator. However, if necessary, one may construct a model having these charges as state variables by introducing a current generator that transfers charge from source to drain internally without producing extra currents in the leads of the device.

On charge nonconservation in FET's

The depth distribution N(x) of Si/sup 29/ ion beam implanted into GaAs for a wide range of implant doses, energies, and SiN randomizing-layer thicknesses is discussed. It is found that the variation of implant angle with position on the wafer (typically encountered in scanned-ion-beam implantation systems) results in significant channeling-induced nonuniformity of the doping profiles, even in some cases where a randomizing layer was used. Because of the existence of exponential tails in virtually all implants, an extension of the standard LSS theoretical profile is necessary for accurate characterization of the implants and prediction of the device parameters. The measured profiles were fitted to two different modified-Gaussian analytical forms: the Pearson four-parameter form, which offers excellent flexibility in fitting arbitrary distributions but is relatively devoid of physical content, and a new three-parameter form that is an extension of a Gaussian to profiles hyperbolic in log N. In almost all cases, the hyperbolic-Gaussian form fits the data as well as the Pearson form, and the hyperbolic-Gaussian form is simpler. Parameters characterizing the implants for both types of fit are presented. >

I.W. Smith

Papers

GaAs FET device and circuit simulation in SPICE

On charge nonconservation in FET's

Channeling, exponential tails, and analytical modeling of Si implants into GaAs