Disclosed are a method, apparatus, and program product for routing an electronic design using double patterning that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patterning, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.

Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning

Disclosed are a method, apparatus, and computer program product for performing interactive layout editing to address double patterning approaches to implement lithography of electronic designs. A spatial query is performed around the shape(s) being created during editing with the distance of allowed spacing in a single mask. If a design error is encountered, corrective editing may occur to correct the error. Checking may occur to make sure that the error detection and corrective actions can be performed interactively.

Method, system, and program product for interactive checking for double pattern lithography violations

Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer method. In one approach, interconnections can be in arbitrary directions. In another approach, interconnections follow grid lines in x and y-directions.

Method, system, and program product for routing an integrated circuit to be manufactured by sidewall-image transfer

The growing demand for electronic devices, smart devices, and the Internet of Things constitutes the primary driving force for marching down the path of decreased critical dimension and increased circuit intricacy of integrated circuits. However, as sub-10 nm high-volume manufacturing is becoming the mainstream, there is greater awareness that defects introduced by original equipment manufacturer components impact yield and manufacturing costs. The identification, positioning, and classification of these defects, including random particles and systematic defects, are becoming more and more challenging at the 10 nm node and beyond. Very recently, the combination of conventional optical defect inspection with emerging techniques such as nanophotonics, optical vortices, computational imaging, quantitative phase imaging, and deep learning is giving the field a new possibility. Hence, it is extremely necessary to make a thorough review for disclosing new perspectives and exciting trends, on the foundation of former great reviews in the field of defect inspection methods. In this article, we give a comprehensive review of the emerging topics in the past decade with a focus on three specific areas: (a) the defect detectability evaluation, (b) the diverse optical inspection systems, and (c) the post-processing algorithms. We hope, this work can be of importance to both new entrants in the field and people who are seeking to use it in interdisciplinary work.

Optical wafer defect inspection at the 10 nm technology node and beyond

New techniques recently developed at the National Institute of Standards and Technology using bright-field optical tools
are applied to signal-based defect analysis of features with dimensions well below the measurement wavelength. A key
to this approach is engineering the illumination as a function of angle and analysis of the entire scattered field. In this
paper we demonstrate advantages using this approach for die-to-die defect detection metrology. This methodology,
scatterfield optical microscopy (SOM), is evaluated for defect inspection of several defect types defined by Sematech on
the Defect Metrology Advisory Group (DMAG) intentional defect array (IDA) wafers. We also report the systematic
evaluation of defect sensitivity as a function of illumination wavelength.
Theoretical simulations are reported that were carried out using a fully three-dimensional finite difference time domain
(FDTD) electromagnetic simulation package. Comprehensive modeling was completed investigating angle-resolved
illumination to enhance the detection of several defect types from the IDA wafer designs. The defect types covered a
variety of defects from the IDA designs. The simulations evaluate the SOM technique on defect sizes ranging from
those currently measurable to those the industry considers difficult to measure. The simulations evaluated both the 65
nm IDA metal-1 M1 trench and the polysilicon stack and more recent 13 nm linewidth logic cells.

The limits and extensibility of optical patterned defect inspection

Considerable effort is directed towards the development of next-generation lithography processes, addressing the need
for transistor densification to meet Moore's Law. The aggressive design rule shrinkage requires very tight process
windows and induces various types of pattern failure with lithography process variations. Since the lithography process
is critical in the wafer fabrication process, the requirements for high sensitivity defect detection in the lithography
process becomes tighter as design rules shrink. Analysis of the root cause of the defects and of their interaction with
various light sources and optics systems configurations for wafer inspection is essential for understanding the detection
limits and requirements from advanced inspection systems targeting future lithography inspection applications.
In this work, we present an analysis of wafer defects light scattering and detection for a variety of 3xnm design rule resist
structures with various polarizations and optics configurations, at the visible, at UV and at DUV wavelengths. The
analysis indicates on the defect scattering and inspection performance trends for a variety of resist structures and defect
types, and shows that control of the polarization of the optical inspection system is critical for enhanced scattering and
detection sensitivity. The analysis is performed also for the 2xnm and 1xnm design rules showing the advantages of
polarized DUV illumination over unpolarized and visible illumination.

Advanced lithography: wafer defect scattering analysis at DUV

Apparatus for imaging a surface, including an acousto-optic (AO) system. The AO system includes an AO element having a radiation input surface and a radiation output surface. The element is configured to receive radio-frequency (RF) pulses and a radiation input at the radiation input surface and to generate traveling beams from the radiation output surface. The AO system also includes an inhomogeneous polarization generator, positioned relative to the AO element so that the AO system outputs traveling inhomogeneously polarized beams. The apparatus includes objective optics which are configured to focus the inhomogeneously polarized beams onto the surface so as to form respective traveling spots thereon; collection optics, which are configured to collect scattered radiation from the traveling spots and to focus the scattered radiation to form respective image spots; and a detector which is arranged to receive the respective image spots and to generate a signal in response thereto.

Scanning microscopy using inhomogeneous polarization

A method and an apparatus that may include optics that is arranged to illuminate a surface of a sample with radiation and to collect reflected radiation from the surface of the sample; wherein the optics includes a pupil that has multiple pupil segments that correspond to different angular regions of collection or illumination; and a detection module arranged to receive the reflected radiation and generate, for each pupil segment, pupil segment detection signals.

Inspection having a segmented pupil

SADP (Self Aligned Double Patterning) is one of the major options to be implemented to bridge the lithography resolution gaps for 40 nm half pitch nodes and below. A natural concern for IC manufacturers when developing and/or implementing this kind of module is defectivity control strategy to ensure all defect sources are understood and an appropriate inspection strategy can be implemented to ensure high die yields. In this paper we will share a comprehensive study done to understand & characterize the major defect types in the SADP module developed by the Maydan Technology Center of Applied Materials. The implications of this work in terms of setting an optimized inspection strategy in the module will be discussed.

From simulation to characterization - integrated approach for Self Aligned Double Patterning defectivity

We present a technique for optimizing advanced optical imaging methods for nanoscale structures, such as those encountered in the inspection of cutting-edge semiconductor devices. The optimization flow is divided to two parts: simulating light-structure interaction using the finite-difference time-domain (FDTD) method and simulating the optical imaging system by means of its optical transfer function. As a case study, FDTD is used to simulate 10-nm silicon line-space and static random-access memory patterns, with irregular structural protrusions and silicon-oxide particles as defects of interest. An ultraviolet scanning-spot optical microscope is used to detect these defects, and the optimization flow is used to find the optimal imaging mode for detection.

Ido Dolev

Papers

Advanced lithography: wafer defect scattering analysis at DUV

Scanning microscopy using inhomogeneous polarization

Inspection having a segmented pupil

From simulation to characterization - integrated approach for Self Aligned Double Patterning defectivity

Simulating semiconductor structures for next-generation optical inspection technologies