Liyan Miao

TL;DR: In this paper, a 300mm baseline process of record using a 12nm half-pitch PS-b-PMMA lamellae block copolymer was established to establish an initial measurement of the defect density due to inherent polymer phase separation defects such as leakage and disclinations.

TL;DR: In this article, the authors investigated the defect densities of various DSA process applications in the context of a 300mm wafer fab cleanroom environment, and reported a defect density process window relative to chemical epitaxial pre-pattern registration lines.

TL;DR: In this paper, the authors conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including 300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for sub-16nm lines and spaces.

TL;DR: In this article, a self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm patterning.

TL;DR: Several wafer level demonstrations are reviewed, all of which use various forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of addressing 15nm technology node requirements and below.