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Ihar Kasko
Researcher at Infineon Technologies
Publications - 6
Citations - 116
Ihar Kasko is an academic researcher from Infineon Technologies. The author has contributed to research in topics: Layer (electronics) & Electrode. The author has an hindex of 4, co-authored 6 publications receiving 116 citations.
Papers
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Patent
Deep alignment marks on edge chips for subsequent alignment of opaque layers
Chandrasekhar Sarma,Ihar Kasko +1 more
TL;DR: In this article, a method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece is described, where the alignment marks are formed in at least one material layer of the semiconductor device.
Patent
Semiconductor arrangement with non-volatile memories
Recai Sezi,Andreas Walter,Reimund Engl,Anna Maltenberger,Christine Dehm,Arkalgud Sitaram,Ihar Kasko,Joachim Nützel,Jakob Kriz,Thomas Mikolajick,Cay-Uwe Dr. Pinnow +10 more
TL;DR: In this article, a semiconductor arrangement comprising at least one nonvolatile memory cell that is provided with a first electrode which consists of at least two layers is described. And a method for producing such a non-volatile cell, and a plurality of inventive memory cells, is presented.
Patent
Methods of patterning a magnetic stack of a magnetic memory cell and structures thereof
TL;DR: In this article, the top magnetic material layer of a magnetic stack is patterned using a hard mask, and a conformal insulating material is deposited over the patterned top magnet material layer and hard mask.
Patent
Halbleiteranordnung mit nichtflüchtigen speichern
Recai Sezi,Andreas Walter,Reimund Engl,Anna Maltenberger,Christine Dehm,Arkalgud Sitaram,Ihar Kasko,Joachim Nützel,Jakob Kriz,Thomas Mikolajick,Cay-Uwe Dr. Pinnow +10 more
TL;DR: In this paper, a Halbleiteranordnung with mindestens einer nichtfluchtigen Speicherzelle, eine erste Elektrode, die einem organischen material, wobei das organische material mit der im unmittelbaren Kontakt stehenden Lage der ersten ElektROde eine Verbindung bildet.
Patent
Tiefe Justiermarken auf Rand-Chips zum anschließenden Ausrichten von opaken Schichten
Ihar Kasko,Chandrasekhar Sarma +1 more
TL;DR: Verfahren zum Herstellen eines Halbleiterelementes (100) as discussed by the authors, wobei: • ein Substrat (102) bereitgestellt wird, welches eine Mehrzahl von Die-Bereichen (105) and mindestens einen Rand-bereich (103) with Gebieten with unvollstandigen Dies oder ungenutzten Substrats enthalt.