Showing papers by "Iouliia Skliarova published in 2011"

Implementation in FPGA of Address-Based Data Sorting

Abstract: The paper describes the hardware implementation and optimization of sorting algorithms that use data items as memory addresses with one-bit flags indicating presence of data. The proposed technique enables such type of address-based sorting to be applied either directly or through tree-walk tables permitting number of bits in sorted data items to be increased by constructing and traversing N-ary trees (N>2) composed of so called no-match and working nodes. The latter are organized in well balanced sub-trees of equal depth. It is allowed more than one data item to be assigned to leaves of working sub-trees and such sets of items are processed by fast acceleration circuits. Experiments and comparisons demonstrate that the proposed technique can be used efficiently in low cost FPGAs.

Acceleration of Recursive Data Sorting over Tree-based Structures

Abstract: The main objective of this paper is to evaluate and improve FPGA-based digital circuits, which implement recursive specifications.Recursive sorting algorithms over binary trees are considered as a case study to evaluate and demonstrate new techniques and theiradvantages. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model ofa hierarchical finite state machine (HFSM). The paper presents analysis and comparison of alternative and competitive techniques fordescribing recursive algorithms in hardware. The experimental results demonstrate that the proposed innovations allow to achieve betterperformance. Obviously, the results of this paper are not limited to recursive sorting alone. They have a wider scope and can be appliedeffectively to numerous systems that implement recursive algorithms over tree-based data structures. Ill. 8, bibl. 10, tabl. 2 (in English;abstracts in English and Lithuanian). http://dx.doi.org/10.5755/j01.eee.113.7.612

FPGA-based systems in information and communication

Abstract: This tutorial is intended to give introduction to FPGA-based systems, to illustrate advantages of these systems in terms of technical characteristics and economic aspects, to demonstrate design steps on practical examples, and to discuss potential benefits and case studies targeted to the scope of the conference. It will be also shown that teaching FPGA-based systems is very important in engineering education and in University of Aveiro (Portugal) it has been supported from 2009 by the Hewlett Packard grant entitled «Use of HP Mobile Technology to Enhance Teaching Reconfigurable Systems for Electrical and Computer Engineering Curricula». The tutorial can also be seen as a dissemination of the results demonstrating how the HP mobile technology has been used to create a stimulating environment to encourage collaborative and interactive learning, to provide better interaction between the students and teachers, to extend opportunities for design space exploration in the scope of reconfigurable systems, to work more efficiently with tutorials, design templates and libraries, to provide for fast exchange of design ideas between the students and the students and teachers, and to ultimately reduce the gap between the industrial requirements and capabilities of engineering training.

Hardware implementation of recursive sorting algorithms

Abstract: The paper describes methods of data sorting in hardware using parallel recursive algorithms over a binary tree. The implementation is based on communicating hierarchical finite state machines interacting with dedicated memories. Distinctive features of the proposed methods are balancing the tree to increase the performance of hardware implementation and the use of sorting networks combined with operations over the tree. Parallel processing is achieved through constructing and traversing different branches of the tree at the same time. The results of prototyping in FPGA and experiments demonstrate applicability and effectiveness of the proposed technique.

High-performance hardware accelerators for sorting and managing priorities

Abstract: The paper describes the hardware implementation and optimization of algorithms that process tree-like data structures which are needed for numerous practical applications in such areas as databases, embedded systems, and networks requiring priority management. The emphasis is done on applications that involve fast processing of new incoming data items, such as resorting. Parallelism is achieved by constructing N binary trees (N>1) and applying concurrent operations to N trees at the same time with the aid of N communicating processing modules. It is shown that the considered technique can efficiently be combined with sorting networks, which gives new potentialities for optimization. Modeling in software, experiments with FPGA-based circuits on different computing platforms, and comparisons with the other known methods demonstrate that the performance is increased significantly. It is also shown that the proposed algorithms are easily scalable.

Processing tree-like data structures for sorting and managing priorities

Abstract: The paper describes the hardware implementation and optimization of algorithms that sort data using tree-like structures combined with sorting networks. The emphasis is done on applications that require dynamic resorting for new incoming data items. Experiments and comparisons demonstrate that the performance is increased compared to other known implementations.

Multilevel models for data processing

Abstract: The paper suggests multilevel models for data processing and demonstrates advantages of such models on examples of data sorting. Three different techniques are discussed, namely graph walk, using tree-like structures and sorting networks. The relevant implementations were done on the basis of hierarchical finite state machines and verified in commercially available FPGAs. Experiments and comparisons demonstrate that the results enable the performance of processing for different types of data to be increased compared to known implementations.

Processing N-ary trees in hardware circuits

Abstract: The paper demonstrates that N-ary trees (N>2) can efficiently be used to model and process data in hardware. It is done through: 1) representation of data by N-ary trees; 2) compact coding of N-ary trees in memory; 3) common methods for data processing based on the model of a hierarchical finite state machine (HFSM). The proposed techniques have the following advantages: 1) similarity of processing N-ary trees with different characteristics such as the size of data M, the value N, and the depth d of trees; 2) fixed number of processing steps from the root to leaves for the given depth d; 3) the ease of reconfiguration (customization) of HFSM for different values of N, d, and M; 4) potential parallel processing of nodes' children. The results of experiments confirm effectiveness of the proposed techniques and their applicability for solving practical problems.

and Managing Priorities

Abstract: The paper describes the hardware implementation and optimization of algorithms that process tree-like data structures which are needed for numerous practical applications in such areas as databases, embedded systems, and networks requiring priority management. The emphasis is done on applications that involve fast processing of new incoming data items, such as resorting. Parallelism is achieved by constructing N binary trees (N)1) and applying concurrent operations to N trees at the same time with the aid of N communicating processing modules. It is shown that the considered technique can efficiently be combined with sorting networks, which gives new potentialities for optimization. Modeling in software, experiments with FPGA­ based circuits on different computing platforms, and comparisons with the other known methods demonstrate that the performance is increased significantly. It is also shown that the proposed algorithms are easily scalable. Keywords-tree-li ke data structures, fast resorting, managing priorities, hierarchical FSMs, parallelization, sorting networks

Recursion and hierarchy in digital design and prototyping: a case study

Abstract: With the constant growth of integration level, today's circuits contain way over millions of gates. This puts forward a fundamental question -- how to efficiently use enormous and continuously rising hardware resources in the design process? This paper describes a reuse technique that can be applied to the design of FPGA-based application-specific digital systems. Reusability is achieved at the level of specifications. The proposed specification and implementation method is based on the model of hierarchical finite state machine (HFSM). This allows to describe fragments (modules) in such a way that the developed algorithm can be composed of either new or previously designed modules providing reuse on project scale.

Simulation environment for visual prototyping of circuits and systems

Abstract: The paper presents results in the following two areas: the visual graphical verification of hardware systems and the synthesis of digital circuits from modular, hierarchical, recursive, and parallel specifications. Within these areas a simulation multimedia environment has been developed and used for verification of the proposed methods that are based on new structural models. The applicability of the environment and the methods is demonstrated through examples.