The discrete cosine transform (DCT), introduced by Ahmed, Natarajan and Rao, has been used in many applications of digital signal processing, data compression and information hiding. There are four types of the discrete cosine transform. In simulating the discrete cosine transform, we propose a generalized discrete cosine transform with three parameters, and prove its orthogonality for some new cases. A new type of discrete cosine transform is proposed and its orthogonality is proved. Finally, we propose a generalized discrete W transform with three parameters, and prove its orthogonality for some new cases. Keywords: Discrete Fourier transform, discrete sine transform, discrete cosine transform, discrete W transform Nigerian Journal of Technological Research , vol7(1) 2012

On discrete cosine transform

Sum of absolute differences (SAD) calculation is one of the most time-consuming operations of video encoders compatible with the high efficiency video coding standard. SAD hardware architectures employ an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper exploits different adder compressors structures into the SAD hardware architecture. The architectures were synthesized to 45-nm CMOS standard cells. Synthesis results show that SAD architecture using 8–2 compressor composed with 4–2 compressors and Kogge–Stone adder in the recombination line reduces power dissipation by 25.5% on average when compared with the SAD architecture using conventional adders from a state-of-the-art synthesis tool. Our throughput analysis shows that the designed SAD units are capable of encoding full HD ( $1920\times 1080$ ) videos in real time at 30 frames/s.

Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design

A cross-layer design space exploration (DSE) method based on a proposed co-simulation technique is presented herein. The proposed method is demonstrated evaluating the impacts on both coding efficiency and power dissipation of applying distinct approximate logic operators in a s $\mu {\mathrm{ m}}$ of absolute differences (SAD) kernel that accelerates an H.265/HEVC (high-efficiency video coding) encoder. The proposed method simulates the gate-level circuit dynamically inside the application, with realistic results of the impact of the adder-tree approximate logic implementation on both quality and encoder bit-rate results. A comprehensive DSE is shown herein, with 13 types of 6 classes of approximate adders in the SAD accelerator hardware blocks. Over 3,000 logic variants of approximations at gate-level were developed. Actual video sequences as inputs to the x265 software encoder are co-simulated, to dynamically capture the video motion-estimation (ME) behavior in the presence of logic approximations. While the prior art that only estimates the impact of the approximate logic on power, area, and quality on static designs with statistical assumptions, which are agnostic to the actual algorithm data-dependent behavior in the application, our method explores accurately the trade-off between power dissipation and coding efficiency dynamically over the entire HEVC encoding. Our approach shows that the lower-part-or and error-tolerant adder I approximate adders, as well as truncation-to-zero deliver better compression-power trade-offs, with substantial differences from the static analysis.

A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders

The High Efficiency Video Coding (HEVC) standard is a new generation video coding scheme, succeeding to H.264/AVC. HEVC requires only 50 % bitrate of H.264/AVC at the same perceptual quality by adopting new coding tools and more flexible block structures. HEVC specifies 35 different intra prediction directions that can be associated to different block sizes. Each possible combination needs to be tested within the Rate Distortion (RD) process to enable selecting the optimal intra mode and block splitting depth. This leads to a significant processing weight and therefore any improvement that might be achieved will bring significative increase in the computational efficiency of the algorithm. This paper proposes a novel intra prediction modes pruning method based on decision trees and a new three-step search algorithm, aiming at achieving higher encoding efficiency compared to the standard--HEVC. This fast algorithm is composed of two algorithms. The first algorithm is a modes pruning algorithm depending on decision trees. We first calculate variances of the above side, the left side and all the reference samples of all the PUs (Prediction Units), which are used to divide the PUs into three groups of different candidate intra prediction modes. The first group only includes Planar mode and DC mode, the optimal mode will be selected from the two modes. The second and third groups include 19 and 35 intra modes, respectively. Then the decision trees are trained using the information obtained previously by the software WEKA. The classification process has an accuracy of 85.29 %. The second algorithm is a three-step search algorithm which is defined to be suitable for prediction units classified into class two and class three after the execution of decision trees. The detailed implementations of three-step search algorithms for prediction units belong to those two classes are subtly different. Experimental results verify that, compared with the reference software HM15.0, on average, the proposed algorithm reduces the encoding time by 37.87 % with a slightly decreasing of BD-PSNR (0.058 dB) and increasing of BD-Rate (1.19 %).

A fast algorithm of intra prediction modes pruning for HEVC based on decision trees and a new three-step search

JPEG Pleno is a standardization framework addressing the compression and signaling of plenoptic modalities. While the standardization of solutions to handle light field content is currently reaching its final stage, the Joint Photographic Experts Group (JPEG) committee is now preparing for the standardization of solutions targeting point cloud and holographic modalities. This paper addresses the challenges related to the standardization of compression technologies for holographic content and associated test methodologies.

JPEG Pleno holography: scope and technology validation procedures

The increasing demand for highly realistic and immersive visual experiences has led to the emergence of richer 3D visual representation models such as light fields, point clouds and meshes. Light fields may be modelled as a 2D array of 2D views, corresponding to a large amount of data, which demands for highly efficient coding solutions. Although static light fields are inherently 4D structures, the coding solutions in the literature mostly employ traditional 2D coding tools associated with techniques such as depth-based image rendering to generate a residual, again to be coded using available 2D coding tools. To address the market needs, JPEG has launched the so-called JPEG Pleno standard, which Part 2 is dedicated to light field coding. The JPEG Pleno Light Field Coding standard includes two coding modes, one based on the 4D-DCT, so-called 4D-Transform mode, and another based on depth-based synthesis, so-called 4D-Prediction. The 4D-Transform coding mode standardizes for the first time a 4D-native light field coding solution where the full light field redundancy across the four dimensions is comprehensively exploited, somehow extending to 4D the 2D coding framework adopted decades ago by the popular JPEG Baseline standard. In this context, this paper describes and analyzes in detail the conceptual and algorithmic design process which has led to the creation of the JPEG Pleno Light Field Coding standard 4D-Transform coding mode. This has happened through a sequence of steps involving technical innovation design and integration where increasingly sophisticated coding tools have been combined and improved to maximize the final rate distortion (RD) performance.

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The JPEG Pleno Light Field Coding Standard 4D-Transform Mode: How to Design an Efficient 4D-Native Codec

State-of-the-art video coding standards adopt large block and transform sizes. Moreover, as resolutions keep growing, there is a trend in adopting even larger structures in future video encoders, resulting in higher complexity. Therefore, the design of energy-efficient architectures for variable block size distortion metrics are key to keep the energy requirements of battery devices under a reasonable budget. The Hadamard-based Sum of Absolute Transformed Differences (SATD) is used as distortion metric in several steps of encoding, increasing the overall encoding efficiency at the cost of rising complexity. In this work, we propose two main approaches for SATD calculation of N × N block sizes. One using a Transpose Buffer (TB) and another one using a Linear Buffer (LB). Furthermore, we synthesized four sizes (4 × 4 up to 32 × 32) of each main SATD architecture to evaluate their area and energy estimates. The results show a large increase in area for TB-SATD, while LB-SATD area increases in a much smaller pace. On the other hand, the TB-SATD synthesized for Low-Vdd/High-Vt show up to be the most energy-efficient architectures for all sizes.

Energy-efficient SATD for beyond HEVC

In this paper we present energy-efficient Hadamard-based Sum of Absolute Transformed Differences (SATD) architectures. We relied on two state of the art methods for SATD, one using the Fast Hadamard Transform (FHT) butterfly and another one using the so-called Transform-Exempted (TE) SATD algorithm. Those were combined with architectural decisions, as the use of a transpose buffer. A total of six Hadamard-based SATD architectures were synthesized for a commercial 45 nm standard cell library. The best energy results are related to TE-SATD architectures: down to 7.62 pJ/SATD in the case of parallel architecture with pipeline. However, considering also the area results when evaluating energy, the best results are achieved when both methods are applied to the transpose buffer base architecture: nearly 10 pJ/SATD with up to 71% smaller area compared with parallel base architectures.

Energy-Efficient Hadamard-Based SATD Architectures

The most energy-hungry step of Video Coding (VC) is the Block Matching Algorithm (BMA), even when a simple similarity metric such as the Sum of Absolute Differences (SAD) is employed. Moreover, with the increasing resolutions supported by state-of-the-art VC standards (H.264/AVC, HEVC and VP9), the SAD must be as energy-efficient as possible to increase the battery lifetime in portable mobile devices. Two well-known techniques to decrease the number of operations in SAD calculation are Pel Decimation and Partial Distortion Elimination (PDE). The energy savings provided by the former are dictated by the chosen decimation ratio and comes with a cost in coding efficiency. For the latter, energy savings have no cost in coding efficiency but are dictated by the video content and search parameters. In this work we present two configurable SAD4×4 architectures: one designed to dynamically operate using one among four Pel Decimation ratios (1∶1, 4∶3, 2∶1 or 4∶1) and the other one able to use PDE in addition to Pel Decimation. We simulated Pel Decimation and PDE behavior during motion estimation using 22 video samples from the Common Test Conditions (CTC) encoded using 4 different quantization parameters (QPs). Thus, this simulation was performed over 5.82×1012 PDE SADs. The Pel Decimation impacts are shown in terms of Bjontegaard Delta (BD)-Rate, ranging from 3.16% (1∶1 ratio) up to 21.94% (4∶1). In addition, we found that by using PDE solely (i.e., without Pel Decimation) one can reduce from 10 to 6.38 (in average) the number of required cycles to calculate one SAD. To show the improvements in terms of energy, we synthesized both presented architectures using a 45nm standard cell library. Finally, the use of PDE can improve energy efficiency more than Pel Decimation alone, without coding efficiency degradation.

Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency

A new image compression standard, known as JPEG Pleno, is currently under its final standardization stage and has been developed by the ISO/IEC JTC 1/SC 29/WG 1 standardization committee. This paper reports the current status of the final draft of JPEG Pleno Part 1, Part 2 and a detailed description of the conformance tests and the reference software under standardization as Part 3 and 4.

Ismael Seidel

Papers

The JPEG Pleno Light Field Coding Standard 4D-Transform Mode: How to Design an Efficient 4D-Native Codec

Energy-efficient SATD for beyond HEVC

Energy-Efficient Hadamard-Based SATD Architectures

Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency

An overview of the emerging JPEG Pleno standard, conformance testing and reference software