High Efficiency Video Coding (HEVC) provides superior coding efficiency than previous video coding standards at the cost of increasing encoding complexity. The complexity increase of motion estimation (ME) procedure is rather significant, especially when considering the complicated partitioning structure of HEVC. To fully exploit the coding efficiency brought by HEVC requires a huge amount of computations. In this paper, we analyze the ME structure in HEVC and propose a parallel framework to decouple ME for different partitions on many-core processors. Based on local parallel method (LPM), we first use the directed acyclic graph (DAG)-based order to parallelize coding tree units (CTUs) and adopt improved LPM (ILPM) within each CTU (DAGILPM), which exploits the CTU-level and prediction unit (PU)-level parallelism. Then, we find that there exist completely independent PUs (CIPUs) and partially independent PUs (PIPUs). When the degree of parallelism (DP) is smaller than the maximum DP of DAGILPM, we process the CIPUs and PIPUs, which further increases the DP. The data dependencies and coding efficiency stay the same as LPM. Experiments show that on a 64-core system, compared with serial execution, our proposed scheme achieves more than 30 and 40 times speedup for 1920 × 1080 and 2560 × 1600 video sequences, respectively.

Efficient Parallel Framework for HEVC Motion Estimation on Many-Core Processors

High Efficiency Video Coding (HEVC) uses a very flexible tree structure to organize coding units, which leads to a superior coding efficiency compared with previous video coding standards. However, such a flexible coding unit tree structure also places a great challenge for encoders. In order to fully exploit the coding efficiency brought by this structure, huge amount of computational complexity is needed for an encoder to decide the optimal coding unit tree for each image block. One way to achieve this is to use parallel computing enabled by many-core processors. In this paper, we analyze the challenge to use many-core processors to make coding unit tree decision. Through in-depth understanding of the dependency among different coding units, we propose a parallel framework to decide coding unit trees. Experimental results show that, on the Tile64 platform, our proposed method achieves averagely more than 11 and 16 times speedup for 1920x1080 and 2560x1600 video sequences, respectively, without any coding efficiency degradation.

A Highly Parallel Framework for HEVC Coding Unit Partitioning Tree Decision on Many-core Processors

The emerging international standard of High Efficiency Video Coding (HEVC) is a successor to H.264/AVC. In the joint model of HEVC, the tree structured coding unit (CU) is adopted, which allows recursive splitting into four equally sized blocks. At each depth level, it enables up to 34 intra prediction modes. The intra mode decision process in HEVC is performed using all the possible depth levels and prediction modes to find the one with the least rate distortion (RD) cost using Lagrange multiplier. This achieves the highest coding efficiency but requires a very high computational complexity. In this paper, we propose a fast CU size decision and mode decision algorithm for HEVC intra coding. Since the optimal CU depth level is highly content-dependent, it is not efficient to use a fixed CU depth range for a whole image. Therefore, we can skip some specific depth levels rarely used in spatially nearby CUs. Meanwhile, there are RD cost and prediction mode correlations among different depth levels or spatially nearby CUs. By fully exploiting these correlations, we can skip some prediction modes which are rarely used in the parent CUs in the upper depth levels or spatially nearby CUs. Experimental results demonstrate that the proposed algorithm can save 21% computational complexity on average with negligible loss of coding efficiency.

Fast CU size decision and mode decision algorithm for HEVC intra coding

This work presents a performance comparison of the two latest video coding standards H.264/MPEG-AVC and H.265/MPEG-HEVC (High-Efficiency Video Coding) as well as the recently published proprietary video coding scheme VP9. According to the experimental results, which were obtained for a whole test set of video sequences by using similar encoding configurations for all three examined representative encoders, H.265/MPEG-HEVC provides significant average bit-rate savings of 43.3% and 39.3% relative to VP9 and H.264/MPEG-AVC, respectively. As a particular aspect of the conducted experiments, it turned out that the VP9 encoder produces an average bit-rate overhead of 8.4% at the same objective quality, when compared to an open H.264/MPEG-AVC encoder implementation - the x264 encoder. On the other hand, the typical encoding times of the VP9 encoder are more than 100 times higher than those measured for the x264 encoder. When compared to the full-fledged H.265/MPEG-HEVC reference software encoder implementation, the VP9 encoding times are lower by a factor of 7.35, on average.

Performance comparison of H.265/MPEG-HEVC, VP9, and H.264/MPEG-AVC encoders

This paper presents a performance evaluation study of coding efficiency versus computational complexity for the forthcoming High Efficiency Video Coding (HEVC) standard. A thorough experimental investigation was carried out to identify the tools that most affect the encoding efficiency and computational complexity of the HEVC encoder. A set of 16 different encoding configurations was created to investigate the impact of each tool, varying the encoding parameter set and comparing the results with a baseline encoder. This paper shows that, even though the computational complexity increases monotonically from the baseline to the most complex configuration, the encoding efficiency saturates at some point. Moreover, the results of this paper provide relevant information for implementation of complexity-constrained encoders by taking into account the tradeoff between complexity and coding efficiency. It is shown that low-complexity encoding configurations, defined by careful selection of coding tools, achieve coding efficiency comparable to that of high-complexity configurations.

Performance and Computational Complexity Assessment of High-Efficiency Video Encoders

The High Efficiency Video Coding standard provides improved compression ratio in comparison with its predecessors at the cost of large increases in the encoding computational complexity. An important share of this increase is due to the new flexible partitioning structures, namely the coding trees, the prediction units, and the residual quadtrees, with the best configurations decided through an exhaustive rate-distortion optimization (RDO) process. In this paper, we propose a set of procedures for deciding whether the partition structure optimization algorithm should be terminated early or run to the end of an exhaustive search for the best configuration. The proposed schemes are based on decision trees obtained through data mining techniques. By extracting intermediate data, such as encoding variables from a training set of video sequences, three sets of decision trees are built and implemented to avoid running the RDO algorithm to its full extent. When separately implemented, these schemes achieve average computational complexity reductions (CCRs) of up to 50% at a negligible cost of 0.56% in terms of Bjontegaard Delta (BD) rate increase. When the schemes are jointly implemented, an average CCR of up to 65% is achieved, with a small BD-rate increase of 1.36%. Extensive experiments and comparisons with similar works demonstrate that the proposed early termination schemes achieve the best rate-distortion-complexity tradeoffs among all the compared works.

Fast HEVC Encoding Decisions Using Data Mining

The High Efficiency Video Coding (HEVC) is an emerging standard that achieves higher encoding efficiency when compared to previous standards such as H264/AVC One key contributor to this improvement is the new intra prediction method that supports a large number of prediction directions at a cost of very high computational complexity This paper presents a fast intra prediction mode decision algorithm, which instead of taking into account only the modes of the neighbor PUs (prediction units) uses edge information of the current PU to choose a reduced set of directions from which the best prediction mode (direction) is finally selected The proposed method provides a decrease of up to 3208% in the HEVC intra prediction processing time, with a little increase in the bit-rate (09% on average) and a negligible reduction in PSNR values

Fast HEVC intra prediction mode decision based on EDGE direction information

The emerging High Efficiency Video Coding (HEVC) standard is expected to require much more processing power than its predecessors due to the higher algorithmic complexity of new coding tools and associated data structures. This paper proposes a novel complexity control method for the near future HEVC encoders running on power-constrained devices. The proposed method is based on a decision algorithm that dynamically adjusts the depth of the Coding Units (CU) defined by quad-tree structures. New evidence about the relationship between CU depth and coding complexity is used to selectively constrain the CU depth in order to not exceed a predefined complexity target. The experimental results show that the encoder computational complexity can be downscaled by up to 60% at the cost of negligible loss of rate-distortion (RD) performance. The proposed method finds application in the near future multimedia portable devices using HEVC codecs.

Complexity control of high efficiency video encoders for power-constrained devices

This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression This architecture is used as the core of a JPEG compressor and is the critical path in JPEG compression hardware The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole architecture is divided into two I-D DCT calculations by using a transpose buffer These parts are described in this paper, with an architectural discussion and the VHDL synthesis results as well The 2-D DCT architecture uses 4,792 logic cells of one Altera Flex10kE FPGA and reaches an operating frequency of 122 MHz One input block with 8/spl times/8 elements of 8 bits each is processed in 252 /spl mu/s and the pipeline latency is 160 clock cycles

Luciano Agostini

Papers

Performance and Computational Complexity Assessment of High-Efficiency Video Encoders

Fast HEVC Encoding Decisions Using Data Mining

Fast HEVC intra prediction mode decision based on EDGE direction information

Complexity control of high efficiency video encoders for power-constrained devices

Pipelined Fast 2-D DCT Architecture for JPEG Image Compression