Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration

Online Fault Tolerance for FPGA Logic Blocks

This article reviews the existing work in self-healing and self-repairing technologies, including work in software engineering, materials, mechanics, electronics, MEMS, self-reconfigurable robotics, and others. It suggests a terminology and taxonomy for self-healing and self-repair, and discusses the various related types of other self-* properties. The mechanisms and methods leading to self-healing are reviewed, and common elements across disciplines are identified.

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Self-healing and self-repairing technologies

We present an integrated approach to on-line FPGA testing, diagnosis and fault tolerance, to be used in high-reliability and high-availability hardware. The testing and diagnostic process takes place in Self-Testing AReas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is tested by roving the STARs across the FPGA. Our approach guarantees complete testing of both logic cells and interconnect with maximum diagnostic resolution. Our multi-level fault-tolerant technique allows using partially defective logic and routing resources for normal operation, providing longer mission life in the presence of faults. In addition, our dynamic fault-tolerant method ensures that spare resources are always present in the neighborhood of the located fault, thus simplifying fault-bypassing. Our complete method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies.

Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems

Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

Field Programmable Gate Array Applications—A Scientometric Review

A wide range of fault tolerance methods for FPGAs have been proposed. Approaches range from simple architectural redundancy to fully on-line adaptive implementations. The applications of these methods also differ; some are used only for manufacturing yield enhancement, while others can be used in-system. This survey attempts to provide an overview of the current state of the art for fault tolerance in FPGAs. It is assumed that faults have been previously detected and diagnosed; the methods presented are targeted towards tolerating the faults. A detailed description of each method is presented. Where applicable, the methods are compared using common metrics. Results are summarized to present a succinct, comprehensive comparison of the different approaches.

A survey of fault tolerant methodologies for FPGAs

Signal generation and analysis are an important part of BIST for analog and mixed-signal systems. An accurate analysis of the spectral content of signals produced by analog components can be accomplished with a digital implementation of a fast Fourier transform (FFT) algorithm. In the past, size and speed have limited the application of such a technique to off-chip test equipment or DSP chips (primarily due to the number of multiplication operations). In this paper, we present an FFT approximation technique suitable for on-chip spectral BIST signal generation and analysis. For signal generation, we show that the noise produced by the approximation technique is under 24.74 dB for a 256 point FFT with a 32 point approximate kernel. For signal analysis, we show that the instantaneous dynamic range (IDR) for the approximation technique is under 21.80 dB for a 256 point FFT with a 32 point approximate kernel. Our techniques have been implemented and demonstrated on a Xilinx Virtex-II FPGA using an off-chip ADC and DAC, and we are currently implementing the technique on an ASIC using a 0.13 /spl mu/m SiGe process for 2-16 GHz applications.

An FFT approximation technique suitable for on-chip generation and analysis of sinusoidal signals

In this paper we present a Fault Tolerant (FT) technique for programmable interconnect on Field Programmable Gate Arrays (FPGAs). Our on-line strategy uses incremental reconfiguration capabilities of FPGAs to avoid faults, and the main advantage of our technique is that it does not require a router at the time FT reconfiguration is performed. Our algorithm generates precompiled FT partial configurations that can be downloaded when faults occur. Since the precompiled partial configurations are stored on a net by net basis, the required storage space and the download time is minimal. We have implemented our technique on the ORCA series FPGAs available from Lucent Technologies, and we demonstrate our technique on a FPGA based, on-line Adaptive Computing System (ACS) implemented with the ORCA FPGAs. Our worst case data indicates we can determine an average of seven alternates per signal net and for most circuits up to ten.

On-line incremental routing for interconnect fault tolerance in FPGAs minus the router

In this paper we analyze the performance penalty of a fault-tolerant (FT) adaptive computing system (ACS) that implements the roving Self Testing AReas (STARs) approach for on-line testing and fault tolerance for FPGAs[1,5]. For most benchmarks, the presence of the STARs increases the critical path delay by 4.6% to 22%, and preallocating spare cells for fault tolerance causes an additional increase of up to 37%. We also present a procedure for estimating the worst case performance penalty caused by an incremental change of an already placed and routed FPGA. This estimate can be used to guide the selection of fault-tolerant reconfigurations to minimize their impact on the system timing. Our results show that the estimate is within 10% of the real delay values.

Performance Penalty for Fault Tolerance in Roving STARs

Intelligent radio frequency (RF) front ends make use of MMIC and MEMS devices to provide a limited range of programmability to what have historically been fixed resistive, capacitive, and inductive impedance matching networks. Many BIST methods for mixed-signal systems can also be used to monitor and provide feedback for the control of such RF systems. For example, spectral techniques can be used to analyze and determine the center frequency of a bandpass filter. Information relative to the center frequency can then be fed back into the system, and adjustments can be made to fine tune the filter. In this paper, we outline our spectral based, mixed-signal approach for monitoring the health of analog and RF components in mixed-signal systems on-chip. In our approach we use well known DSP techniques based an the FFT for on-chip signal generation and analysis. We reduce required hardware by using the same functional block to analyze analog output signals that we use to generate m tone stimulus signals. By providing an on-chip functional test capability, we also reduce the test time required on expensive ATE. Our techniques have been prototyped and demonstrated on a Xilinx Virtex-II FPGA using an off-chip ADC and DAC, and we are currently implementing the technique on an ASIC using a 0.13 /spl mu/m process with target execution speeds of 2-16 GHz.

J.A. Cheatham

Papers

A survey of fault tolerant methodologies for FPGAs

An FFT approximation technique suitable for on-chip generation and analysis of sinusoidal signals

On-line incremental routing for interconnect fault tolerance in FPGAs minus the router

Performance Penalty for Fault Tolerance in Roving STARs

A monolithic spectral BIST technique for control or test of analog or mixed-signal circuits