The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.

Cache memory self test

The realization of a space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of very large scale integration (VLSI) circuits. This paper presents a new zero-aliasing compaction approach of test data outputs with an application specifically targeted to digital embedded cores-based system-on-chips (SOCs), which facilitates the design of such space-efficient BIST support hardware. The suggested technique takes advantage of some well-known concepts of conventional switching theory, together with those of strong and weak compatibilities of response data outputs in the selection of specific gates for merger of an arbitrary but optimal number of output bit streams from the module under test (MUT), based on optimal generalized sequence mergeability, as developed and applied by the authors in earlier works. This is novel in the sense that zero aliasing is realized without any modification of the MUT, while a maximal compaction is achieved in almost all cases in reasonable time utilizing some simple heuristics. The method is illustrated with design details of space compactors for ISCAS 85 combinational benchmark circuits using simulation programs ATALANTA, FSIM, and COMPACTEST, confirming the usefulness of the approach for its simplicity, resulting low area overhead, and full fault coverage for single stuck-line faults, thereby making it suitable in a VLSI design environment. With advances in computational resources in the future, the heuristics adopted in the design algorithm may be further improved upon to significantly lower the simulation CPU time and storage

Space compactor design in VLSI circuits based on graph theoretic concepts

As the electronics industry continues to grow, technology feature sizes continue to decrease, and complex systems and levels of integration continue to increase, the need for better and more effective methods of testing to ensure reliable operations of chips, the mainstay of today's all digital systems, is being increasingly felt One obvious way to significantly improve the testability of digital VLSI circuits and save testing time is to use built-in self-testing (BIST), where the basic idea is to have the chip test itself BIST is a design methodology that combines the concepts of built-in test (BIT) and self-test (ST) in one, termed BIST This technique generates test patterns and evaluates test responses inside the chip system, and has been widely used in many commercial VLSI products with appreciable success The subject paper endeavors to present a comprehensive overview of the general methodology of BIST from its various perspectives, and in the sequel attempts to relate its significance in the particular context of modern embedded cores-based system-on-chip (SOC) technology

Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware

Detection of open defects in static random access memory (SRAM) cells, including those causing data retention faults (DRFs), is known to be difficult and time consuming. This paper proposes a novel design-for-test (DFT) technique that allows SRAMs to be tested at full speed for these defects. As a result, it achieves not only significant test time reduction but also full coverage of open defects, including those undetectable to previous solutions. The proposed technique is referred to as predischarge write test mode (PDWTM). Implementation of the proposed technique requires little design effort and imposes negligible hardware and performance penalties. Furthermore, the proposed technique can be easily merged with any March algorithm, thus resulting in full DRF and other SRAM cell open defect coverage. The proposed technique has been validated by SPICE simulation using both low-power and high-speed SRAM cells.

Fast detection of data retention faults and other SRAM cell open defects

The realization of space-efficient support hardware for built-in self-testing (BIST) is of great significance in VLSI circuits design. New approaches to designing aliasing-free space compaction hardware are proposed in the subject paper for testing cores-based system-on-chip (SOC) for single stuck-line faults, extending the well-known concepts of conventional switching theory, viz. those of cover table, frequency ordering commonly utilized in the simplification of switching functions, and of incompatibility relation to generate maximal compatibility classes using graph theoretic concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper provides briefly the mathematical basis of selection criteria for merger of an optimal number of outputs of the circuit under test (CUT) to achieve maximum compaction ratio in the design, along with some partial simulation results on ISCAS 85 combinational benchmark circuits with programs ATALANTA and FSIM. The advantages of the suggested approaches are evident in achieving zero aliasing without any CUT modifications, while keeping the area overhead and signal propagation delay relatively low, besides their applicability with both deterministic compacted and pseudorandom test patterns

https://www.site.uottawa.ca/%7Epetriu/TrIM06-SpaceCompactorVLSI.pdf

Space Compactor Design in VLSI Circuits Based on Graph Theoretic Concepts

Refinements to testing strategies for earlier microprocessor on-chip caches led to fast, efficient characterization and debugging of the smaller geometry PA8500 cache.

J. Fleischman

Papers

Design of cache test hardware on the HP PA8500