Journal ArticleDOI
Design of cache test hardware on the HP PA8500
J. Bralich,J. Fleischman +1 more
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TLDR
Refinements to testing strategies for earlier microprocessor on-chip caches led to fast, efficient characterization and debugging of the smaller geometry PA8500 cache.Abstract:
Refinements to testing strategies for earlier microprocessor on-chip caches led to fast, efficient characterization and debugging of the smaller geometry PA8500 cache.read more
Citations
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Patent
Cache memory self test
TL;DR: In this article, the authors present a self-testing approach to test the cache as a whole (i.e., RAM, CAM, and comparators together) in the test mode, where cache writes are absolutely addressable.
Journal ArticleDOI
Space compactor design in VLSI circuits based on graph theoretic concepts
TL;DR: A new zero-aliasing compaction approach of test data outputs with an application specifically targeted to digital embedded cores-based system-on-chips (SOCs), which facilitates the design of such space-efficient BIST support hardware.
Journal ArticleDOI
Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware
TL;DR: The subject paper endeavors to present a comprehensive overview of the general methodology of BIST from its various perspectives, and in the sequel attempts to relate its significance in the particular context of modern embedded cores-based system-on-chip (SOC) technology.
Journal ArticleDOI
Fast detection of data retention faults and other SRAM cell open defects
TL;DR: A novel design-for-test (DFT) technique that allows SRAMs to be tested at full speed for these defects, which achieves not only significant test time reduction but also full coverage of open defects, including those undetectable to previous solutions.
Proceedings ArticleDOI
Space Compactor Design in VLSI Circuits Based on Graph Theoretic Concepts
TL;DR: New approaches to designing aliasing-free space compaction hardware are proposed in the subject paper for testing cores-based system-on-chip (SOC) for single stuck-line faults, extending the well-known concepts of conventional switching theory.
References
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Book
Testing Semiconductor Memories: Theory and Practice
TL;DR: Memory modeling functional testing: reduced functional RAM chip model Functional RAM chip testing functional ROM chip testingfunctional memory array testing functional memory board testing electrical testing: parametric testing dynamic testing on chip testing conclusions: address line scrambling various proofs software package.
Journal ArticleDOI
Using march tests to test SRAMs
TL;DR: A unified notation is presented for static random access memory (SRAM) fault models and fault tests for these models, and empirical results showing the fault coverage of the different test enable SRAM users to choose the fault models of interest as well as the test.
Proceedings ArticleDOI
March LR: a test for realistic linked faults
TL;DR: An overview of the most important and commonly used fault models, including the industry's popular disturb fault model, are given and a methodology to design tests for realistic linked faults is presented, resulting in the new tests March LR, March LRD and March LRDD.
Proceedings ArticleDOI
Testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor
Marc E. Levitt,S. Nori,S. Narayanan,G.P. Grewal,L. Youngs,A. Jones,G. Billus,S. Paramanandam +7 more
TL;DR: The testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor have helped enormously in achieving the time-to-volume goals and hence the overall success of the product.
Journal ArticleDOI
Random pattern testing versus deterministic testing of RAMs
TL;DR: The number of (random) patterns required for random testing of RAMs (random-access memories), when classical fault models including pattern-sensitive faults are considered is determined, and Markov chains are a powerful tool for this purpose.