High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described.

Time interleaved converter arrays

A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9- mu m CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm/sup 2/ and dissipates 240 mW. >

/pdf/a-10-b-20-msample-s-analog-to-digital-converter-2hcsguqnq3.pdf

A 10-b 20-Msample/s analog-to-digital converter

A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.

https://www.ee.columbia.edu/~kinget/EE6312_S04/project/refs/lewis_pipelined_ad_jssc_dec_1987.pdf

A pipelined 5-Msample/s 9-bit analog-to-digital converter

The author examines the effect of the stage resolution on some important characteristics of monolithic, pipelined, multistage, analog-to-digital converters (ADCs) with identical stages for video-rate applications. These characteristics are the linearity, speed, area, and power dissipation. It is found that although large stage resolution is desirable from a linearity standpoint, the effect of stage resolution on linearity is small if the ADC uses redundancy and digital correction and if the magnitude of the interstage gain is at least two. Also, minimizing the stage resolution maximizes the conversion rate and minimizes both the die area and the power dissipation. >

Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications

A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC. A 20-MHz sampling rate with 350-mW power dissipation from a single 5-V power supply has been realized. Integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion has been achieved through intensive transistor dimension optimization applied to the comparator circuit, instead of employing an offset canceling technique.

A CMOS 8-Bit High-Speed A/D Converter IC

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.

J.G. Peterson

Papers

A monolithic video A/D converter