The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is accelerating introduction of new technologies to extend complementary MOS (CMOS) down to, and perhaps beyond, the 22-nm node This acceleration simultaneously requires the industry to intensify research on two highly challenging thrusts: one is scaling CMOS into an increasingly difficult manufacturing domain well below the 90-nm node for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications, and the other is an exciting opportunity to invent fundamentally new approaches to information and signal processing to sustain functional scaling beyond the domain of CMOS This article is focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures This paper provides a brief introduction to each of the new nonclassical CMOS structures This is followed by a presentation of one scenario for introduction of new structural changes to the MOSFET to scale CMOS to the end of the ITRS A brief review of electrostatic scaling of a MOSFET necessary to manage short channel effects (SCEs) at the most advanced technology nodes is also provided

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

SUMMARY AND CONCLUSIONS Scaling CMOS to and beyond the 22-nm technology node(requiring a physical gate length of 9-nm or less) will probablyrequire the introduction of several new material and struc-tural changes to the MOSFET to sustain performance increas-es of 17% per year and to manage SCEs. Material changes willinclude strained silicon n- and p-channels and a new gatestack including a high-k dielectric and a metal gate electrode.Structural changes could include fully depleted UTB SOI sin-gle-gate MOSFETs, perhaps followed by fully depleted UTBdouble-gate structures. Attaining the performance require-ments for the final node for high performance applicationscould further require channels providing quasiballistic carriertransport, or very low-resistance source/drain contacts provid-ed by Schottky metal electrodes. The materials and structuralchanges actually introduced to advanced process technologieswill depend both on their readiness for manufacture and theirvalue in improving performance in the ultra-scaled devices.For example, a high-

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Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance

A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process' allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enable ables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.

Silicon-on-Nothing (SON)-an innovative process for advanced CMOS

In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15-/spl mu/m PMOS devices showing substantial efficiency in reducing SCE and I/sub OFF/ current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

A novel device architecture called SON (silicon on nothing) is proposed, allowing extremely thin buried oxides and silicon films to be fabricated and thereby provide better resistance to short channel effects (SCE) and DIBL than any other device architecture. SON devices are shown to present excellent I/sub on//I/sub off/ trade-off, V/sub th/ roll-off suppression down to 15 nm channel length, and to be free from the shortcomings of conventional SOI, such as self-heating, high S/D series resistances, and expensive SOI substrates since SON devices are fabricated on bulk silicon.

SON (silicon on nothing)-a new device architecture for the ULSI era

We propose a new process of selective lateral under-etching of bi-layered Si/SiGe gates, aimed at the formation of well-controlled notches. Weak Ge mole fraction (/spl les/30%) and moderate notch depth render the notch formation compatible with standard CMOS process, and prevent dispersions. The latter, in the case of a shallow notch (/spl les/25 nm) are even smaller than in reference Si-gate devices without a notch. Higher commutation speed, better transconductance and better SGE/DIBL immunity are demonstrated experimentally on notched gate devices.

Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS

The proposed SONCTION (SilicON Cut-off juncTION) process consists in tailoring of the junction depth by physical removing of a "sacrificial" bottom part of the junction. This becomes possible since the junction is implanted within a bilayer of SiGe capped with silicon. It enables a selective removal of the SiGe layer from underneath the Silicon, thus physically reducing the junction depth. The cavity left out by the removed SiGe is refilled with oxide, thus preventing the smearing out of the junction profile which therefore can be doped to a high level and comfortably annealed. As the SiGe and Si layers are fabricated by epitaxy, feasibility and perfect reproducibility of thin junctions, such as a few nm, is ensured.

Heavily doped and extremely shallow junctions on insulator by SONCTION (SilicON Cut-off juncTION) process

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15- m PMOS devices showing substantial efficiency in reducing SCE and current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.

J. Galvier

Papers

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

SON (silicon on nothing)-a new device architecture for the ULSI era

Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS

Heavily doped and extremely shallow junctions on insulator by SONCTION (SilicON Cut-off juncTION) process

Dielectric pockets  a new concept of the junctions for deca-nanometric CMOS devices

J. Galvier

Papers

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

SON (silicon on nothing)-a new device architecture for the ULSI era

Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS

Heavily doped and extremely shallow junctions on insulator by SONCTION (SilicON Cut-off juncTION) process

Dielectric pockets &#150; a new concept of the junctions for deca-nanometric CMOS devices

Dielectric pockets a new concept of the junctions for deca-nanometric CMOS devices