The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is accelerating introduction of new technologies to extend complementary MOS (CMOS) down to, and perhaps beyond, the 22-nm node This acceleration simultaneously requires the industry to intensify research on two highly challenging thrusts: one is scaling CMOS into an increasingly difficult manufacturing domain well below the 90-nm node for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications, and the other is an exciting opportunity to invent fundamentally new approaches to information and signal processing to sustain functional scaling beyond the domain of CMOS This article is focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures This paper provides a brief introduction to each of the new nonclassical CMOS structures This is followed by a presentation of one scenario for introduction of new structural changes to the MOSFET to scale CMOS to the end of the ITRS A brief review of electrostatic scaling of a MOSFET necessary to manage short channel effects (SCEs) at the most advanced technology nodes is also provided

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

SUMMARY AND CONCLUSIONS Scaling CMOS to and beyond the 22-nm technology node(requiring a physical gate length of 9-nm or less) will probablyrequire the introduction of several new material and struc-tural changes to the MOSFET to sustain performance increas-es of 17% per year and to manage SCEs. Material changes willinclude strained silicon n- and p-channels and a new gatestack including a high-k dielectric and a metal gate electrode.Structural changes could include fully depleted UTB SOI sin-gle-gate MOSFETs, perhaps followed by fully depleted UTBdouble-gate structures. Attaining the performance require-ments for the final node for high performance applicationscould further require channels providing quasiballistic carriertransport, or very low-resistance source/drain contacts provid-ed by Schottky metal electrodes. The materials and structuralchanges actually introduced to advanced process technologieswill depend both on their readiness for manufacture and theirvalue in improving performance in the ultra-scaled devices.For example, a high-

/pdf/toward-the-introduction-of-new-materials-and-structural-5checsrym5.pdf

Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance

A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process' allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enable ables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.

Silicon-on-Nothing (SON)-an innovative process for advanced CMOS

In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

"Extreme environments" represents an important niche market for electronics and spans the operation of electronic components in surroundings lying outside the domain of conventional commercial, or even military, specifications. Such extreme environments would include, for instance, operation to very low temperatures (e.g., to 77 K or even 4.2 K), operation at very high temperatures (e.g., to 200/spl deg/C or even 300/spl deg/C), and operation in a radiation-rich environment (e.g., space). We argue that the unique bandgap-engineered features of silicon-germanium heterojunction bipolar transistors offer great potential to simultaneously satisfy all three extreme environment applications, potentially with little or no process modification, ultimately providing compelling cost advantages at the IC and system level.

On the Potential of SiGe HBTs for Extreme Environment Electronics

A novel device architecture called SON (silicon on nothing) is proposed, allowing extremely thin buried oxides and silicon films to be fabricated and thereby provide better resistance to short channel effects (SCE) and DIBL than any other device architecture. SON devices are shown to present excellent I/sub on//I/sub off/ trade-off, V/sub th/ roll-off suppression down to 15 nm channel length, and to be free from the shortcomings of conventional SOI, such as self-heating, high S/D series resistances, and expensive SOI substrates since SON devices are fabricated on bulk silicon.

SON (silicon on nothing)-a new device architecture for the ULSI era

A 200 mm 0.35 /spl mu/m silicon-germanium heterojunction bipolar transistor (SiGe HBT) technology involving epitaxially-aligned polysilicon emitters is described. The devices are shown to combine the high speed performances typical for poly-Si emitter SiGe base devices (f/sub max/ up to 70 GHz) and the low 1/f noise properties of monocrystalline emitter structures (noise figure-of-merit KB as low as 7.2/spl times/10/sup -10/ /spl mu/m/sup 2/). Statistical current gain data are used to demonstrate the manufacturability of this innovative SiGe HBT technology.

A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters

A low complexity 0.35 /spl mu/m SiGe HBT technology, using a quasi self-aligned emitter/base structure on a non-selective Si/SiGe epitaxial base, is described. Excellent high frequency performances (f/sub max/ up to 71 GHz) are obtained, opening the way to a highly manufacturable SiGe BiCMOS technology.

C. Morin

Papers

SON (silicon on nothing)-a new device architecture for the ULSI era

A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters

A high performance low complexity SiGe HBT for BiCMOS integration

Single-wafer Si and SiGe processes for advanced ULSI technologies

Epitaxial growth of SiGe layers for BiCMOS applications