Radio frequency integrated circuits (RFICs) are the building blocks that enable every device from cable television sets to mobile telephones to transmit and receive signals and data. This newly revised and expanded edition of the 2003 Artech House classic, "Radio Frequency Integrated Circuit Design", serves as an up-to-date, practical reference for complete RFIC know-how. The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results. By emphasizing working designs, this book practically transports readers into the authors' own RFIC lab so they can fully understand how these designs function. This title is suitable for radio frequency integrated circuit (RFIC) design engineers; radio systems architects; researchers and developers of RFIC technology; and, graduate level electrical engineering students.

Radio Frequency Integrated Circuit Design

This paper describes a fractional-N PLL IC based on a new digital quantizer that replaces the DeltaSigma modulator (DeltaSigmaM) used in conventional designs. In combination with a charge pump offset technique and a sampled loop filter the new quantizer enables state-of-the-art fractional spur performance without sacrificing BW.

Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL

This paper demonstrates that spurious tones in the output of a fractional-N PLL can be reduced by replacing the DeltaSigma modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms, and presents a phase noise cancelling 2.4 GHz ISM-band CMOS PLL that demonstrates the techniques. The PLL has a 975 kHz loop bandwidth and a 12 MHz reference. Its phase noise has a worst-case reference spur power of - 70 dBc and a worst-case in-band fractional spur power of -64 dBc.

Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional- N PLL

This paper presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected phase error is then coarsely compensated by dynamically changing the divide ratio of the frequency divider. The proposed method allows the PLL to maintain a small phase error throughout the frequency acquisition process, thereby reducing the settling time. To further enhance the locking speed, an auxiliary charge pump is employed to supply currents to the loop filter during the fast-locking mode to facilitate a rapid frequency acquisition. The proposed technique is incorporated in the design of a 5-GHz PLL. Fabricated in the TSMC 0.18-μm CMOS technology, the whole PLL dissipates 11 mA from a 1.8-V supply. The measured settling time is considerably improved over previous bandwidth-switching method. At 5.34 GHz, the phase noise measured at 1-MHz offset is -114.3 dBc/Hz, and the reference spurs at 10-MHz offset are lower than -70 dBc.

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

Phased arrays are multiple antenna systems capable of forming and steering beams electronically using constructive and destructive interference between sources. They are employed extensively in radar and communication systems but are typically rigid, bulky and heavy, which limits their use in compact or portable devices and systems. Here, we report a scalable phased array system that is both lightweight and flexible. The array architecture consists of a self-monitoring complementary metal–oxide–semiconductor-based integrated circuit, which is responsible for generating multiple independent phase- and amplitude-controlled signal channels, combined with flexible and collapsible radiating structures. The modular platform, which can be collapsed, rolled and folded, is capable of operating standalone or as a subarray in a larger-scale flexible phased array system. To illustrate the capabilities of the approach, we created a 4 × 4 flexible phased array tile operating at 9.4–10.4 GHz, with a low areal mass density of 0.1 g cm−2. We also created a flexible phased array prototype that is powered by photovoltaic cells and intended for use in a wireless space-based solar power transfer array. By combining a CMOS-based integrated circuit with flexible and collapsible radiating structures, a scalable phased array architecture can be fabricated that has an areal mass density of only 0.1 g cm−2.

A flexible phased array system with low areal mass density

A phase-locked loop (PLL) frequency synthesizer with an on-chip passive discrete-time loop filter is reported in this paper. The closed loop is robust stable, and a fast switching speed is achieved by creating a stabilization zero in the discrete-time domain. The circuit implementations and system-level analysis results of the proposed architecture are presented. Techniques and design considerations are presented to overcome several potential problems of the proposed architecture, such as finite lock-in range, translation of voltage-controlled oscillator noise into in-band phase noise, and spur degradation due to clock feedthrough of the sampling switch. A 2.4 GHz prototype frequency synthesizer for Bluetooth applications was developed in a 0.25-/spl mu/m CMOS process. The measured results agree with theoretical predictions and demonstrate its high performance.

J.M. Huard

Papers

A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-/spl mu/m CMOS