Journal ArticleDOI
A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-/spl mu/m CMOS
B. Zhang,P.E. Allen,J.M. Huard +2 more
TLDR
In this article, a phase-locked loop (PLL) frequency synthesizer with an on-chip passive discrete-time filter is reported, and the closed loop is robust stable, and a fast switching speed is achieved by creating a stabilization zero in the discrete time domain.Abstract:
A phase-locked loop (PLL) frequency synthesizer with an on-chip passive discrete-time loop filter is reported in this paper. The closed loop is robust stable, and a fast switching speed is achieved by creating a stabilization zero in the discrete-time domain. The circuit implementations and system-level analysis results of the proposed architecture are presented. Techniques and design considerations are presented to overcome several potential problems of the proposed architecture, such as finite lock-in range, translation of voltage-controlled oscillator noise into in-band phase noise, and spur degradation due to clock feedthrough of the sampling switch. A 2.4 GHz prototype frequency synthesizer for Bluetooth applications was developed in a 0.25-/spl mu/m CMOS process. The measured results agree with theoretical predictions and demonstrate its high performance.read more
Citations
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Book
Radio Frequency Integrated Circuit Design
John Rogers,Calvin Plett +1 more
TL;DR: The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results as discussed by the authors, which practically transports readers into the authors' own RFIC lab so they can fully understand how these designs function.
Proceedings ArticleDOI
Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL
TL;DR: This paper describes a fractional-N PLL IC based on a new digital quantizer that replaces the DeltaSigma modulator (DeltaSigmaM) used in conventional designs that enables state-of-the-art fractional spur performance without sacrificing BW.
Journal ArticleDOI
Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional- N PLL
TL;DR: It is demonstrated that spurious tones in the output of a fractional-N PLL can be reduced by replacing the DeltaSigma modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter.
Journal ArticleDOI
A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops
TL;DR: In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process, and the detected phase error is coarsely compensated by dynamically changing the divide ratio of the frequency divider.
Journal ArticleDOI
A flexible phased array system with low areal mass density
Mohammed Reza M. Hashemi,Austin Fikes,Matan Gal-Katziri,Behrooz Abiri,Florian Bohn,Amirreza Safaripour,Michael D. Kelzenberg,Emily L. Warmann,Pilar Espinet,Nina Vaidya,Eleftherios Gdoutos,Christophe Leclerc,Fabien Royer,Sergio Pellegrino,Harry A. Atwater,Ali Hajimiri +15 more
TL;DR: By combining a CMOS-based integrated circuit with flexible and collapsible radiating structures, a scalable phased array architecture can be fabricated that has an areal mass density of only 0.1 g cm−2.
References
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Journal ArticleDOI
Charge-Pump Phase-Lock Loops
TL;DR: This paper analyzes typical charge-pump circuits, identifies salient features, and provides equations and graphs for the design engineer.
Journal ArticleDOI
A fully integrated CMOS DCS-1800 frequency synthesizer
Jan Craninckx,Michiel Steyaert +1 more
TL;DR: In this paper, a prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 /spl mu/m CMOS process without any external components.
SP 23.5: A Fully Integrated CMOS DCS-1800 Frequency Synthesizer
J. Craninckx,M. Steyaert +1 more
TL;DR: In this article, a 4/sup th/order type-2 charge-pump PLL frequency synthesizer for the DCS-1800 system in a standard 0.4 /spl mu/m CMOS process without external components is presented.
Journal ArticleDOI
A 2.4 GHz CMOS transceiver for Bluetooth
Hooman Darabi,Shahla Khorram,E. Chien,Meng-An Pan,Stephen Wu,Shervin Moloudi,John Leete,Jacob Rael,Masood Syed,R. Lee,Brima Ibrahim,M. Rofougaran,Ahmadreza Rofougaran +12 more
TL;DR: A fully integrated CMOS transceiver tuned to 2.1 GHz consumes 46 mA in receive-mode and 47mA in transmit-mode from a 2.7 V supply and delivers a GFSK modulated spectrum at an output power of 5 dBm.
Patent
Charge pump phase locked loop
TL;DR: In this article, a phase lock loop circuit with a phase detector, a charge pump, an active filter, and a voltage-controlled oscillator is described. But the phase detector is not considered in this paper.