A novel surface passivation tailored to a two-dimensional array of small-area, gate-controlled InSb photovoltaic diodes fabricated on etch-thinned bulk InSb wafers, with backside illumination, is presented. The surface passivation is based on a controlled surface treatment that reduces the native oxide and is followed by photon-assisted deposition of SiO/sub x/. Thinned bulk n-type InSb with

Surface passivation of backside-illuminated indium antimonide focal plane array

Properties of CdTe/InSb heterostructures grown on (111)B InSb substrates by molecular beam epitaxy are reported X‐ray diffraction and uv reflectance measurements were used to judge the quality of epitaxy for layers grown under various conditions Auger depth profile analysis revealed a sharp CdTe/InSb interfacial region of less than 250 A for depositions at 220 °C Detailed capacitance‐voltage measurements yielded interface‐state densities of 14–28×1011 cm−2 eV−1 (near midgap) for these preliminary samples, indicating that improved metal‐insulator‐semiconductor structures on InSb may be possible using this lattice‐matched heterojunction surface passivation scheme

Properties of CdTe/InSb heterostructures prepared by molecular beam epitaxy

Hysteresis free capacitance‐voltage (C‐V) characteristics of SiO2/InSb metal‐insulator‐semiconductor (MIS) diodes are attained by introducing an in situ Br vapor etching technique into the fabrication process. Interface state density is also reduced by using this technique. It is found that following vapor etching, MIS C‐V characteristics are strongly dependent on both the SiO2 film deposition temperature and oxygen flow rate. The optimum condition for SiO2 film deposition to obtain hysteresis free C‐V curves and an interface state density of ≤1×1011 cm−2 eV−1 is determined for InSb MIS diodes. The area of the typical optimum conditions for MIS diodes is located in the oxygen flow rate range of 5–6 cc/min and the deposition temperature range of 200–210 °C. The refractive indices of SiO2 films are 1.44–1.45, the breakdown field strengths are more than 2×106 V/cm, and the dielectric constants for 1 MHz are typically 4.7 at 77 K, respectively.

Hysteresis free SiO2/InSb metal‐insulator‐semiconductor diodes

Fast infrared imaging spectroscopy technique (FIIST)

We report on analysis and comparison of the dark current characteristics between InAs p‐n and p‐i‐n diodes at the temperature range from 30 to 300 K. The situation that the dark current is completely due to the bulk instead of the surface leakage is made sure by passivation treatment. The experimental results agree well with a tunnel diode model in which the p‐n and p‐i‐n diodes are described, respectively, with a linear electrical field and a constant electrical field. The diffusion current in our diodes is dominated by the electron diffusion in the p‐type material. Through this model and detailed analysis, we conclude that the tunneling current can be suppressed with an intrinsic layer and a low n‐type doping density while the diffusion current can be decreased with a high p‐type doping density. The advantage of the p‐i‐n structure is not only to cut down the tunneling current but also to increase the uniformity. In terms of this model, a new p‐i‐n diode is designed to dramatically increase its zero‐bias resistance area product and improve the detector performance.

Analysis of the dark current in the bulk of InAs diode detectors

InSb semiconductor technology required for infrared-detector-array fabrications is described. High-quality MOS, MOSFET, and linear and two-dimensional (2D) CID devices have been successfully fabricated. Interface-state densities of the MOS capacitors were determined to be less than 5 × 1010cm-2. eV-1, respectively. These results suggest that self-scanned monolithic arrays could be fabricated. The performance of linear and 2D CID arrays were evaluated in terms of detectivity (D*) and responsivity ( R ). The average D*of a 64- element line array was measured to be 3.4 × 1011cm. Hz1/2. W-1which is 70 percent of that of "background-limited-performance" (BLIP) operation. The R was 1 × 10-5V/photon with 10-percent uniformity. The D*and R were also obtained for a 32 × 32 2D array.

Technology development for InSb infrared imagers

This paper describes the factors governing the Performance Efficiency (PE) of Indium Antimonide Charge Injection Devices (CID) arrays. Factors influencing PE in both line and area arrays are considered and compared to experimental results. An important factor re-lates to the signal charge loss of a dual gate array operating in the charge sharing mode (CSM). The chief advantages of the CSM are that it overcomes charge transfer problems that might be present in practical arrays, and it is believed to be radiation damage resistant. The chief limitation is that only the charge residing under the sensing gate of the dual gate site is read out. This loss can be lessened by designing the sensing gate to be a large fraction of the total storage area. Performance data of lx32, lx64 line arrays, 24x16 and 32x32 dual gate area arrays are presented. Line arrays FE up to 56 percent, responsivity variation below 10 percent, and D* of about 3x1011 cm HZ½/watt have been measured.© (1979) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Performance Efficiency Of InSb Charge Injection Devices (CID)

A high-speed readout scheme for the single-gate charge injection device (CID) linear array using DC-coupled injection (DCI) is described. In contrast to the conventional readout techniques with AC-coupled injection (ACI), DCI provides better time management in reading out the signal charge. Lower device lag is achieved by the longer injection time facilitated by DCI for a given elemental readout cycle. >

High-speed sequential readout for infrared CID arrays with DC-coupled injection

The read-and-clear technique for a single-gate charge-injection-device (CID) array that eliminates the readout lag in the voltage-type sensing mode is discussed. The readout physical mechanisms along with characteristics of the device as a photon detector are analyzed based on a piecewise linear charge-voltage (Q-V) model. The readout scheme decouples the function of CID readout from that of refreshing the pixel storage capacity following injection pulses. Consequently, readout lag is eliminated, and a low-noise equivalent charge through minimized readout capacitance is achieved. In addition, the scheme facilitates a simple implementation of background charge skimming. Empirical results on an InSb CID linear array that in good agreement with theoretical predictions are presented. >

J.M. Swab

Papers

Technology development for InSb infrared imagers

Performance Efficiency Of InSb Charge Injection Devices (CID)

High-speed sequential readout for infrared CID arrays with DC-coupled injection

A voltage-type single-gate CID readout: read and clear-analysis, modeling, and experiment